• State
  • Locked Locked
  • Replies 6 replies
  • Subscribers 22 subscribers
  • Views 967 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

LMK04828: Making Dynamic Digital Delay work

LMK04828: Making Dynamic Digital Delay work reliably

Michael Abbott
Prodigy 220 points

Part Number: LMK04828

Now that I have DDD working, I am finding that its operation is unreliable.   I am running the following test sequence repeatedly (step forwards one tick, step backwards one tick):

PLL[121] <= 33
PLL[122] <= 33
PLL[141] <= 10
PLL[142] <= 01

PLL[121] <= 22
PLL[122] <= 22
PLL[141] <= 10
PLL[142] <= 01

It doesn't take very many repetitions for a step to be missed, sometimes just the one exchange above is enough to slip phase.

Is this supposed to work reliably, am I doing it wrong?

My best theory so far is that CNTH/CNTL = 2/2 doesn't work reliably.  Certainly Table 4 on p.28 of SNAS703 or Table 3 on p.40 of SNAS605AR has unusual looking values for dividers less than 5 ... but unfortunately this table only shows numbers for phase delay, not phase advance.  I've not yet tested whether advancing phase works reliably.

Should this work reliably, or is my divider of 5 too small for reliable dynamic digital phase advance?

  • 0
    Prodigy 220 points
    Can you please confirm that reliable operation of Dynamic Digital Delay requires CNTH >= 2 and CNTL >= 3 (or whatever the true constraint is).
    I can work with this if this is the true constraint, but I do need to know!
    Thank you.
  • 0 in reply to Michael Abbott
    TI__Expert 5370 points
    Dear Michael,

    I have assigned this question to an expert on this device. thank you for your patience.

    Regards, Simon.
  • 0 in reply to Michael Abbott
    TI__Expert 8865 points
    Hello Michael
    You will have to program the divider values as specified in the table 3 on page 40 of the datasheet for Dynamic digital delay to work properly.
    2/2 is not valid combination. Programming the _CNTH & _CNTL as per the table, the timings are ensured for Dynamic digital delay to work reliable.
    Best regards
    Puneet
  • 0 in reply to Puneet Sareen
    Prodigy 220 points
    The table only covers retarding clock phase, not advancing the clock phase.
  • 0 in reply to Michael Abbott
    TI__Expert 8865 points

    Hi Michael,

    Have you programmed the DCLKoutx_DDLYd_CNTH/_CNTL and the DCLKoutx_DDLY_CNTH/_CNTL with the same values? This is a requirement for Dynamic digital delays.

    Best regards

    Puneet

  • 0 in reply to Puneet Sareen
    Prodigy 220 points

    Man, you are clutching at straws.  You've already asked this question of me upthread (this is a post to a related question), and yes, the answer is yes, I do set these fields.

    Let me point out that at this point this is now only a question of documentation.  To fix the documentation for this part TI needs to clarify:

    1. The status of the two documents that appear to cover the LMK04828, in particular does SNAS703 obsolete SNAS605AR?  If so, where is the VCO range for the LMK04828 (non -EP) documented?  As far as I can tell the -EP is identical to the B part (which I think I have) except for a slightly different range of VCO frequencies.
    2. Table 4 (p.28 SNAS703) is a pretty dumb way of saying: add or subtract 1, except if the result is too small, add another clock divider, and then divide by 2 and split the result evenly.  You need to explicitly say what "too small" is here; I'm inferring that 4 is too small.  I'm guessing that the folk who actually know and understand this stuff aren't anywhere near this conversation!
    3. Is the last paragraph of p.28 really saying that I can only move the phase in one direction?  It appears to suggest that I can't change phase shift direction without a resync; is this for real?