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LMX2492EVM: Tolerance on LMX2492EVM Phase Detector Frequency

Part Number: LMX2492EVM
Other Parts Discussed in Thread: PLLATINUMSIM-SW

Hi all!

I'm using a DDS to generate a 50 MHz sine wave that I provide to my LMX2492EVM OSCin. I use the internal doubler to get the signal up to the required 100 MHz phase detector frequency.

This has worked well up until now, however another part of my project would be significantly improved if I generated a 51.282 MHz sine wave instead, leading to a 102.564 MHz phase detector frequency.

Is this tolerable and what are the ramifications in terms of performance? I appreciate that there are passive filters on the evaluation board that will only work within a particular band.

Thanks for the help!

  • Hi Darryn,

    You can use Pll Sim (www.ti.com/tool/pllatinumsim-sw) to check the resultant loop bandwidth and phase margin. When you increase the phase detector freq, the loop bandwidth will increase and in general you will get better in-band phase noise.
  • Hi Noel,

    Thank you for your quick response. I will check pllatinumsim-sw out shortly. I would just like to reiterate that I'm using the evaluation board and that its datasheet specifies a phase detector frequency of 100 MHz. I'll be very happy if I can achieve better performance using a higher frequency, but am confused why a band of acceptable frequencies wasn't specified if this was the case?

    Once again, thanks for your response.
  • Hi Darryn,

    A PLL will lock as long as VCO/N = fpd.
    If fpd is changed, you can also adjust N to maintain the above relationship.
    When you design a loop filter, you specify the loop bandwidth, phase margin, fpd, charge pump current, etc.
    once the loop filter is fixed, if you change fpd or charge pump current, you will get a different loop bandwidth and phase noise.
  • Thanks for the help Noel, that clears things up.

    Kind Regards