LMX2594: Acceptible LMX2594 Input Clock

Ken White

Part Number: LMX2594

Dean,

Is there a specification in the LMX2594 data sheet that determines the minimum input clock jitter or precision above which the device is not able to achieve phase SYNC or lock? I.e. percent of clock period or ppm, etc. I ask this because we are attempting to lock to an intermediate PLL-based device which conforms to the following JEDEC Standard No. 82-31, Table 83 attached below. So far, we are able to successfully lock to the 1.2GHz input clock to this device, but not to its output clock with the specifications in Table 83. I'm suspicious that the added jitter is the culprit. If so, can the loop filter be adjusted to accommodate this additional jitter?

Thanks,

- Ken

Table83.pdf

over 7 years ago

0 Dean Banerjee over 7 years ago

TI__Mastermind 28031 points

Ken,

If OSC2X=0, then the LMX2594 looks only at the rising edges of the input signal, if OSC2X=1, then it looks at rising and falling edges. So duty cycle should only matter if you are using OSC2X (maybe also if MULT>1).

We don't have any data on how bad jitter has to be for the PLL to not actually lock, but pretty bad. In general, if the input reference is noisy, you can reduce the loop bandwidth and this will clean it up somewhat.

However, there is also the VCO calibration, which tells the VCO what frequency band and amplitude settings to use. If the input reference has really high jitter, then theoretically it could fool the VCO to calibrate to the wrong band. once this happens, you are stuck in the wrong band until you tell the device to re-calibrate. This being said, I have never actually seen this happen.

Regards,

Dean

Clock & timing

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LMX2594: Acceptible LMX2594 Input Clock