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LMK04828: multi-lmk synchronization using Sync signal

art arty
Prodigy 140 points
Part Number: LMK04828

I have 5 boards with lmk04828 on each. I also have 10 MHz aligned clocks to each board. I need to synchronize outputs of these synthesizers.

I decided to use them in nested 0-delay loop mode with these parameters:

I also decided to use Sync in edge-sensitive (1 shot) mode.

Here are some questions:

1. Should I land the Sync rising edge in 100 ns window of 10 MHz CLKin1 or in 0.4 ns window of 2500 MHz VCO (I mean windows free of setup and hold intervals)?

2. What is the minimal duration of Sync?

3. Should I use normal or re-clocked Sync?

4. Can I get the full version of this document?lmk_SYNC.pdf

5. What are setup and hold times for Sync in this mode (at least roughly)?

6. Would I get +-1 VCO cycle error for different LMKs' output clocks aligning, or it will be more?

7. Can I use LVPECL signal to CLKin1 input, or it should be sine?

  • 0
    TI__Genius 9920 points
    Hi Art,
    I can answer you question 7.
    CLKin1 input can accept LVPECL AC coupling signal.
  • 0
    TI__Mastermind 28550 points

    art arty said:
    1. Should I land the Sync rising edge in 100 ns window of 10 MHz CLKin1 or in 0.4 ns window of 2500 MHz VCO (I mean windows free of setup and hold intervals)?

    In your 0-delay configuration using SYSREF for feedback.  There are not timing requirements to get a SYSREF signal aligned with any of your other LMK04828 devices for JESD204B purposes.  Meaning to align the LMFC.  Even if the SYSREF happens at another SYSREF 10 MHz edge, from JESD204B perspective the LMFC woudn't know the difference.  Just that it is aligned later than the other devices.

    If you need to have the SYSREF go to your DAC & FPGA clocks at the same moment in time, then you would need to align to the 2500 MHz VCO period... which is going to be hard to do over temperature and such.

    However I have a recommendation I'll get to shortly as you lead into my recommendation with a future question.

    art arty said:
    2. What is the minimal duration of Sync?

    For this purpose, I'll recommend the 25 ns given for RESET on digital input timing spec.

    art arty said:
    3. Should I use normal or re-clocked Sync?

    I recommend using re-clocked Sync.

    art arty said:
    5. What are setup and hold times for Sync in this mode (at least roughly)?

    When using re-clocked SYSREF(SYNC) mode using 10 MHz SYSREF, the period is 100 ns.  If you allow for 10 ns setup and hold time you should have plenty of margin to achieve determinism.

    art arty said:
    6. Would I get +-1 VCO cycle error for different LMKs' output clocks aligning, or it will be more?

    Using this method, I expect you would be able to get +/- 0 VCO cycles.  Because the clocks are aligned through 0-delay of PLL1, the phase variation through PLL1 will impact the relationships of your output clock, this variation can be different for different charge pump current settings of PLL1, but in general around 200 ps over temperature/part/voltage.  As your devices will probably see approximately the same temp (i.e. not -40 and +85 at same time), and voltage ideally regulated similarly would reduce this variation.

    art arty said:
    7. Can I use LVPECL signal to CLKin1 input, or it should be sine?

    No problem with LVPECL.  Sharp edges are generally better for meeting the slew rate.  It is also possible to DC couple into CLKinX deferentially by keeping Vcm around the self bias voltage.

    73,
    Timothy

  • 0 in reply to Timothy T
    Prodigy 140 points
    Thanks for your answer, Tim, that helped me a lot
    My main task is to synchronize outputs of DACs that located on different boards (I have enough time to do that). Each board has its own LMK, so I decided that I should synchronize clock outputs of all LMKs. Should I assert Syncs simultaneously to all LMKs, or it is not necessarily? If it is not, can I synchronize all the LMKs just by toggling SYNC_POL bit on each LMK at different times?
  • 0 in reply to Shawn Han
    Prodigy 140 points
    Hi Shawn,
    Thanks for your answer
  • 0 in reply to art arty
    TI__Mastermind 28550 points
    Hello Art,

    From JESD204B perspective, you can just assert sync by toggling SYNC_POL bit at different times since you have 0-delay keeping things synchronized at 10 MHz. All LMFC will be aligned as SYSREF period = some multiple of LMFC period.

    Depending on the application requirements and what you are syncing would dictate if SYSREF pulses at different times is sufficient or not. For example some devices may have an NCO which gets reset with SYSREF. Best correlation between devices would occur if the SYSREF happened at the same time all devices.

    73,
    Timothy