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Original question:

LMX2594: PFD-VCO-Crosstalk

LMX2594: LMX2594

ldx dfdx
Intellectual 400 points

Part Number: LMX2594

Hi,

       When I let  LMX2594 work in  Integer-N mode with Phase-Sync enabled,I find the PFD spur is about -46dBc，and   Integer-N mode with Phase-Sync disabled, the PFD spur is about -76dBc。The OSCIN frequency is 100MHz ，PFD is 50MHz  with Phase sync enabled.

  • 0
    TI__Mastermind 18070 points
    Hello,

    The change of PFD spur level may be because of PFD frequency change after checking the sync mode. Can you try setting a lower PFD frequency at first so that it does not change after sync pin is enabled?

    Also, try not using output divider if possible, i.e., make output frequency greater than 7500MHz. This way the "flex_IncludedDivide" will remain 1 after sync mode is checked.

    What's your Oscin frequency and output frequency? Did you make any modifications compared to default setup? I can try to replicate your problem if more details are provided.

    Regards,
    Hao
  • 0 in reply to Hao Z
    Intellectual 400 points
    Hi,
    In two cases with phase sync enabled and phase sync disabled, the SFDR is -46dBc and -76dBc, respectively.
    The OSCin is 100MHz，the output is 4000MHz， PFD=50MHz with phase sync mode enabled，and PFD=100MHz without phase sync enabled.
  • 0 in reply to ldx dfdx
    TI__Mastermind 18070 points
    Hello Xiandao,

    Please allow me some time for the measurement. I'll probably get back to your in a few hours.

    Regards,
    Hao
  • 0 in reply to Hao Z
    TI__Mastermind 18070 points
    Xiandao,

    I'm not seeing the -46dBc spur after setting VCO_PHASE_SYNC to 1. Can you send me your Ticspro configuration file (File -> save) and measurement snapshot?

    In the meantime, you can check if you have a clean reference by using another OSCin source.

    Regards,
    Hao
  • 0 in reply to Hao Z
    Intellectual 400 points

    lmx2594_cfg.rar

    Hi,

        Please see the attachment for the configuration file。it's not convenient to measure this clock right now..But it  seems look like the  following  reslult

  • 0 in reply to ldx dfdx
    TI__Mastermind 18070 points

    Hi Xiandao,

    I agree that there is a high spur (not as high as -46dBc in my measurement, though. What I saw was close to -56dBc for 4GHz output). The reason is that the loop filter on the EVM board is quite wide, because it was designed for optimum jitter performance in integer mode. Therefore, it does not have as good spur suppression outside of the band. In order to better suppress the spurs, narrower loop bandwidth is needed. Since the roll-off slope of the loop filter is about -40dB/dec, if the loop bandwidth is halved, the PFD spur can be reduced by 12dB. If you reduce the phase margin, the roll-off rate can be further increased. Please refer to the below file for measurement results of wide loop bandwidth board (default version) versus that of the board which has a narrower loop bandwidth. To test the effect of reducing loop bandwidth on spur suppression, you can simply narrow the loop bandwidth by reducing the charge pump current. But ultimately, the loop filter should be re-designed. Please understand that different use cases require different loop filter designs for optimum performance. To design loop filter, use our free simulation tool Platinumsim http://www.ti.com/tool/PLLATINUMSIM-SW. 

    Ticspro setup.pptx

  • 0 in reply to Hao Z
    Intellectual 400 points

    Hi,

       Thank you for your detailed reply.According to forth slide in the ppt attached,it seems that the phase margin of the narrow bandwidth board is not enough.

  • 0 in reply to ldx dfdx
    TI__Mastermind 18070 points
    Xiandao,

    Yes you are right, the board I used for that measurement has a tight phase margin. So that board was configured for some other purposes and its phase margin is small. But the point that I was trying to make was that, the PFD spur is within the loop and can simply be reduced by tightening loop bandwidth. It is not something that is outside of the loop and hard to optimize. You can adjust the loop dynamics without reducing the phase margin too much.

    Regards,
    Hao