LMK04832: LMK04832 for jitter sensitive clock distribution

We are designing a jitter sensitive clock distribution circuit and have to generate three clocks:

-          CLK100 = LVPECL, 100MHz fixed

-          CLK10 = LVCMOS, 10MHz fixed

-          SYNC100 = LVPECL, 10ns pulses with a variable frequency = 10MHz/n (n = integer, 1-255)

The jitter on the load of CLK100 and SYNC100 has to be max 2psRMS and of CLK10 max 5psRMS.  Skew between all three clocks at the load end must be <|1ns|.

Attached is our current concept. The idea is to use the LMK04832 to generate three clocks: 100MHz, 10MHz and 50MHz. The 50MHz is actually a series of 10n pulses therefore we want use an FPGA which enables timely Buffer1 and create the required 10ns pulse frequency for the SYNC100 signal. The frequency of SYNC100 can be changed by the FPGA enable time points. In the attachment is also a timing diagram of all signals in the current concept.

The PLL has to accept at least three 10MHz clock sources (redundancy) and switch over between inputs glitch free, depending on desired input priority order. One clock comes from a CXO, one from a LVCMOS source and one from a sine wave source with variable voltage levels (200mVpp to TTL). For this input we wand use LTC6957 to convert the voltage level (improve rise time).

We have four issues at the moment:

1. Would you recommend LMK04832 for this application?
2. Which mode on LMK04832 would you propose for our application (DUAL PLL, SINGLE PLL, With External VCO …)?
3. We need at the loads a skew of <|1ns| between all clocks. The used buffers (buffers 6-8 in our concept) have an output-to-output skew of max 75ps. Therefore the LMK04832 clock outputs must have askew of <|900ps|. Is my understanding correct that without any delay register setting all outputs of LMK04832 have an initial skew of typ 100ps to each other? The low initial skew is important to us. We want avoid any output skew adjustments by register settings during mass production.
4. At the moment we planning to use NB6L14 from onsemi as buffer1 (please see our concept). The task of buffer 1 is to work as an “AND gate” for 10ns pulses from LMK04832. Because the application is very jitter sensitive and the NB6L14 has an additive jitter of 1nsRMS we are also looking for other component, which can be used here and has lower additive jitter. Can you recommend something better?

Thank you in advance.Clock_concept_2018.12.20_overview.pdf