• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 22 subscribers
  • Views 1011 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

LMK04828: How to sync two LMK04828 outputs?

LMK04828: MULTICHIP SYNCHRONIZATION about LMK04828

Wong
Intellectual 570 points

Part Number: LMK04828

I need four LMK04828 chip,but how to MULTICHIP SYNCHRONIZATION about  LMK04828?

  • 0
    TI__Genius 9920 points

    Hi William,

    This post could help you.

    With below topology , a 1:n clock buffer for VCXO could make more slave LMK04828 PLL2 synchronized.

    in your case, there are 1 master LMK04828 (PLL1 + PLL2 + VCXO) and 3 slave LMK)4828 (PLL2 only).

    Noticed all PLL2 should work in 0-delay mode.

    Regards,

    Shawn