LMX2592: Reading back registers over SPI

I am designed an FPGA SPI interface to connect to the LMX2592.   TheLMX2592 data sheet is not clear if the register data output on the MUXout pin is changed on the rising or falling edge of the CLK signal when doing a read cycle.   The data sheet merely says "readback serial data will be output starting at the 9th clock."   The  "Register Readback Timing Diagram" (Figure 21)  seems to suggest the data changes on falling edges of the 8th CLK  cycle apparently contradicting the text.  Can anyone please clarify ?