Other Parts Discussed in Thread: ADS4225, CDCM6208V2G, CDCM6208
Hi, i have been studying the CDC7005 way of operation and i am having difficulty understanding how the REF_IN (reference clock) is used. I get it that as soon as it is used the VCXO is outputing a frequency that is times the divider of the CDC7005. What about real-world usage? Let's say that CDC7005 + VCXO is used as an ADC clock. Does the REF_IN of the CDC7005 need to be driven by a near-ideal signal clock source that costs $10K ?
The ADC i am targetting is the ADS4225 12bit 125MS/s. My concern focuses on the jitter of the clock signal that will drive the ADC's clock. I do not want to degrade the SNR and add noise >1/2 LSB.
Also, is there anything wrong in using a software radio ADC in a DSO project? I mean, the bandwidth is huge. I will not be using the full bandwidth, maybe 100MHZ-200MHZ (-3dB).
Can the REF_IN be driven by a noisy FPGA clock where clearly i can set it up to any frequency (within a valid range off course)?
Can the REF_IN be driven by a crystal oscillator which has a relatively limited noise & jitter?
Can you pls suggest other options driving the REF_IN?
Could the CDCM6208V2G be a more suitable solution for my case because it provides an all-in-one solution?
My real goal is to generate a 124.8MHz clock, drive it through a narrow band-pass crystal filter and then pass it to the ADC.
Will the resulting clock @ 124.8 MHz from the CDCM6208V2G be clean enough to prevent degradation of the 12bit ADC SNR? Will i still have use a crystal filter (band-pass) to further decrease jitter noise?
Any help will be appreciated
Best regards
Manos
