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Original question:

Kpfd and vco cap

Custom PLL design

Pankaj Chugh
Prodigy 240 points


Hey Dean,

Thanks for insightful replies.

Could you please share your thoughts with me regarding final 2 design questions or could you give pointers.

Let us say I use 3.3nF capacitor for C1.C2 is even bigger.  WIll I have to do a ON-CHIP or OFF_CHIP Loop Filter. Because, on chip -cap will be huge in terms of area. Kindly, advise.

Also, does PLLatinum sim account for variation of gm of transistor. How much is the variation of specifications of jitter in percentage wise in PLLatinum sim reported jitter values and actual jitter achieved in circuit including inductor noise, gm of transistors etc Any thoughts and suggestions.

Thanks for your time.

  • 0
    TI__Guru** 110790 points
    Hi Pankaj,

    The first question is more a chip design question, I am afraid this is not the scope of this forum. Anyway, in general, I would say if the PLL is for generic use (i.e. the output frequencies are not pre-defined for some specific use cases), the loop filter should be off-chip. It is because you don't know how many poles are needed as well as the capacitor values.
    PLL Sim is a tool designed to assist customers to design the loop filter for our parts. It is not an advanced simulation tool like ADS. You may need to use another tool to help your chip design.