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CDCE62002: About Timing Requirements in the datasheet

user5850039
Prodigy 215 points

Part Number: CDCE62002

Hi,

Two parameters are described in the datasheet as following.

I think that the parameters shows same frequency, however there are two representation " fREF-Diff IN-DIV" and "fREF-Diff REF-DIV".

Which one is correct?.

What block the frequency applied to, pre-divider or ref-divider?

Thank you

  • 0
    TI__Genius 16845 points

    Both parameters are correct. The max spec"fREF-Diff REF-DIV" is half of "fREF-Diff IN-DIV" because the pre-divider of set to 1 rather than 2.
    The input divider can be determined by datasheet Table 5.

    Kind regards,
    Lane

  • 0 in reply to Lane Boyd
    Prodigy 170 points

    I am confused.  I need the frequency conversion from 297MHz to 148.5MHz. However the PLL can not be locked using the parameters that Frequency Planner generated.

    Refer to the following file. I would like you to make sure the spec of the dividers.

    /cfs-file/__key/communityserver-discussions-components-files/48/Maximum-Divider-Frequency.pdf

    Best Regards.

  • 0 in reply to Masaaki MURAI
    TI__Mastermind 28590 points
    Hello Masaaki-san,

    It appears the divider specs are correct in the datasheet as Lane pointed out.

    However the EVM tool is not programming the dividers properly.
    (1) the first divider must be set to /2 to meet the divider frequency spec and
    (2) the maximum phase detector frequency for this device is 40 MHz as given by the specification fCPmax, so when the 297 MHz goes straight through to the PLL, it will fail to lock.

    It appears the frequency planner after calculation shows the correct phase detector frequency, but after applying the solution, it does not update the divide values. Thank you for bringing this bug to our attention.

    In your programming, please adjust to program the pre divider to /2 (R0, bit 9 = 1).

    73,
    Timothy