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I have a customer who would like to leverage the TLP5100 as a really long watchdog timer. (100s – D2=0, D1=1, D0=0)
He is planning to manipulate PGOOD, TCAL and MOS_DRV such that in his system the MCU will be powered ON immediately after PGOOD goes high and while MOS_DRV is high TCAL is LOW. His goal is to remove power from his system if the DONE signal is not toggled within 100s by leveraging the datasheet specifications of MOS_DRV going LOW and TCAL pulsing HIGH should DONE not be toggled high. He would then return PGOOD to 3.3V and start the cycle again. Theory being that this would power cycle his MCU.
The questions comes to play about the internal state machine. If he does toggle DONE before 100s after PGOOD goes HIGH can he expect the following behavior:
Counter reset back to 0 giving him 100s before MOS_DRV and TCAL change states
Can we expect TCAL to stay LOW and MOS_DRV to remain HIGH during this toggle event?
Thank you!
Thank you Rob,
Can you sat if this is an OK use case or not? Sounds like we don't like it since it violates, "The DS states that the time between MOS_DRV going low, and the rising edge of DONE must be at least 100ns wide. This indicates that DONE cannot be asserted before MOS_DRV goes low."
Thanks!
Hi Rob,
I am using TPL5100 as a watchdog. I have configured D0,D1,D2 as high so I have 1024s timer. Currently, my application is sending DONE pulse (High->Low) every 20 seconds and I expect after 1024 sec, it will not reset DRV signal. In my case, irrespective of DONE signal, after 1024s out HW is getting resetted due to TPL5100.
Can you provide more details how we can implement watchdog using TPL5100.