LMX2491: Reopen discussion of best crystal drive to synthesizer chip

Hello Dean:

Thanks for the quick reply. 

I would like to use the LTC6957 buffer instead of cheap inverters, since it is purpose designed to be both fast and low noise while squaring up a crystal output.  Its additive phase noise is lower than that of a quite good crystal oscillator out to about 40kHz offset, and my zone of interest on the current design is well below that.  But, the part is expensive and limited to 3.3V, where it might be driving a very large current into the LMX2491 reference input.  If padded, then it is driving a large current into the pad resistors. 

Can you say if the reference input to the LMX2491 is a diff pair with the kind of diode clipping shown in Figure 4 (page 7) of the report I attached?  That is the structure Linear is using.  This seems quite important to designing an optimum driver that generates high dv/dt, without drawing a lot of current that puts a lot of 25MHz to 100MHz noise on a low noise supply. 

Thanks,

Farron

Hello Dean:

Not hearing back in a few days, I assume you are probably waiting permission to disclose the circuit structure of the LMX2491 crystal reference input processing.  Hopefully that can happen, as it appears essential to have it for optimum crystal driver design.  

Since you recommended the Vectron VC-708 as a reference that limits phase noise degradation due to high driver dv/dt, Texas Instruments has in the past clearly considered the same problem set I am now pointing out.  The VC-708 output is in LV-PECL form (low voltage positive emitter coupled logic with differential output).  This has these advantages:

1.  Fast rise time at 1ns or faster.

2.  Limited voltage swing at about 800mV on each differential output that will not turn on two clipping diodes in series, or only lightly turn on a single diode.

3.  Resulting dv/dt of 0.8V/ns per channel, or 1.6V/ns effective differential dv/dt.  It's fast, though only half the 3V/ns recommended in the LMX2491 data sheet. 

4.  Being current steered logic with nearly constant current draw, does not pull sharp spikes of current from the low noise supply, thus it avoids inducing a lot of voltage noise on the supply.  

This is architecturally exactly in line with the solution I was arriving at.  However, the VC-708 is about 10dB inferior in close in phase noise to some other low cost crystal oscillators of this class.  Also, it draws about 50mA, which is a characteristic of PECL.  Some crystal oscillators with this output form draw as much as 100mA.  Their high power is to drive 50 ohm clock distribution in differential form, at which they excel.  But, this capability is overkill if all the clock has to do is drive the high-Z crystal input pins of a synthesizer chip that is physically placed right next to the crystal oscillator. 

For the synthesizer application, the PECL output form is both a little slower than desired and much higher power consumption than desired.  An ideal form would provide its limited swing to avoid input diode clipping, at higher dv/dt, and with much lower power consumption. 

It appears that an ideal form does not yet exist in the industry.  I was trying to approach it with the lower voltage, differential, moderately padded CMOS form in the report I attached opening this thread.  How well that form can approach ideal depends on the input structure of the reference input circuitry, which is why I am hoping that can be disclosed. 

Since the phase noise degradation for poor crystal dv/dt can be as bad as 17dB according to TI's own data, this is a significant problem.  I might mention that including crystal dv/dt effects on the PLL noise in PLLatinum Sim would appear to be necessary to have accurate noise simulation.  Including the additive noise of the buffering that appears necessary to get higher dv/dt from currently available rather slow dv/dt coming right out of the crystal oscillators would also be necessary for the noise simulation to get full accuracy. 

I will be mentioning this situation in terms of available parts and simulation for Part 4 of my MW&RF series on low noise synthesizer design, which needs to be turned in within two weeks.  In the concluding Part 5, which finishes the series off with examples, I will be showing implementation.  A top RF text author has also recently contacted me for permission to use some of the material from this series in a book to be completed in June.   We can certainly do a better job of presenting Texas Instruments synthesizers relative to this problem if the input structure of the crystal input pins can be disclosed.

Regards,

Farron 

Hi Dean:

OK, thanks for trying. 

This has turned out to be a much trickier situation to get to the bottom of than you would guess going in.  But, it seems like what I have is about as close to ideal as I can get with low cost and without more information, so I'll go forward with it. 

I'll leave this trail temporarily open, and close it next week if burning questions do not arise. 

Thanks,

Farron