LMK04828: Cascaded 0-Delay with CLKout6

Hello Eldrick,

Jhoneldrick Millares said:

What is the difference between the two 0-delay modes? (Cascaded vs Nested). It seems in nested mode, the VCXO will not be deterministic to the CLKin or CLKouts, Why would this mode be used over cascaded?

Nested gives the best input to output phase variation because only the APLL1 phase detector is between reference and output.

Cascaded doesn't have as good of input to output phase variation because both APLL1 and APLL2 phase detector is between reference and output.  However the VCXO is now deterministic to input/output.

You can run Nested + Cascaded to obtain the benefits of both.

Jhoneldrick Millares said:

Is it possible to adjust the "K" parameter in JESD204B such that my SYSREF frequency is equal to my OSCin reference frequency? The XO operates at 122.88 MHz. With an LMFS = 2441, and a sampling rate of 245.76 MSPS, if I choose K = 2, I could achieve a maximum SYSREF frequency of 122.88 MHz. This would thus allow me to use my current hardware for 0-delay mode.

I'm not as familiar with the JESD204B alphabet soup of parameters, but I expect yes, you should be able to adjust the parameters to achieve this.  However your ability to do this may depend on the flexibility or the data mode you chose from your JESD204B device.

Jhoneldrick Millares said:

Finally, in 0-delay mode it seems that there are a few options for reference in feedback - SYSREF, CLKout6, CLKout8, and External. I currently have an unused CLKout6 - could I configure these dividers to generate a 122.88 MHz clock, use it as feedback in 0-delay mode, and achieve deterministic phase relationships for my CLKins and CLKouts?

Yes.  After a sync all these phases are deterministic, so using CLKout6 for 0-delay will give desired determinism for all other clocks synchronized provided CLKout6 frequency results in GCD(clock input frequency, clock output frequency) == clock input frequency and gcd(feedback frequency, gcd(all other clock output frequencies)) = feedback frequency.  Which in general means clock frequency for feedback is lowest frequency.

Even if your not using CLKout6 you can turn the output channel on (leave the output driver off) and use this for 0-delay feedback.  The advantage of using an unused clock (or clock for which phase is of no concern) is you can manipulate the phase of all other clocks wrt to input by adjusting the delays on CLKout6.

73,
Timothy

Jhoneldrick Millares said:

What is the significance of having the VCXO phase determinism if CLKin and CLKout are phase deterministic already?

If you are using OSCout in your system and would like it to be deterministic with the CLKouts you would like this.

Jhoneldrick Millares said:

Related to the question 3 I asked above - if SYSREF had a lower frequency than the clock generated at CLKout6, and I used CLKout6 as the feedback in 0-delay, could I still expect phase determinism for the SYSREF?

It would depend on your input frequency.  Exmple: if you had a 100 MHz input and a  100 MHz CLKout6, you would have phase determinism for the 100 MHz clock and clocks for which GCD(100 MHz, xxx MHz) = 100 MHz.  If you also have a SYSREF of 10 MHz, you would have phase determinism because there would always be some 100 MHz rising edge with your 10 MHz edge because GCD(100 MHz, 10 MHz) = 10 MHz.  The problem would be if you wanted phase determinism between the 10 MHz SYSREF clocks of *two different* LMK devices.  In this case with a 100 MHz reference and even if using a 10 MHz feedback, there would be 10 possible phase relationships due to the division of 100 MHz / 10 = 10 MHz.  To achieve determinism in this case, you would need to provide a reference of 10 MHz and use the SYSREF for feedback.  Using CLKout6 at 100 MHz would once again result in 10 possible phase relationships.

Jhoneldrick Millares said:

Is this phase determinism important in the JESD204B standard in achieving deterministic latency?

In general no.  Provided you are clocking your logic device and converter for example from the same LMK04828, the phase determinism to the reference doesn' t matter.  However of you have *two or more* LMK devices clocking logic devices/converters... then the simplest way for them to all to have the same LMFC clock (as reset by SYSREF) would be to use 0-delay where reference frequency = SYSREF frequency = feedback frequency.

If this distributed system is required and providing the SYSREF frequency as reference is problematic, then you can run the LMK device in 0-delay mode, using SYSREF divider as feedback where SYSREF divider produces the same frequency as reference to LMK.  Set the SYSREF mode re-clocked.  Now you can use an upstream LMK device to provide a reference clock and SYSREF clock to CLKin0 so that the SYSREF will be determinstically re-clocked through to the outputs.

73,
Timothy