LMX2595: Does ‘full assist’ require an initial calibration?

Hi Dean,

One of the first PLL ICs I ever evaluated was the LMX2352. I remember your book was a great resource for my initiation into working with PLLs.  Thanks for the reply on this one.

I created a test to record the VCO_SEL, VCO_CAPCTRL, and VCO_DACISET for all the tune frequencies I intend to use (8 – 15 GHz, 10 MHz steps). I will set the associated FORCE bits high and program these values directly to see how fast I can tune.

I measured unassisted tune times between 100 – 400 us (< 1 kHz error) using the loop filter that was shipped with the eval board (200 MHz PFD, 15 mA Icp). I’d like to tune in less than 100 us across the band, so I’m hoping bypassing the VCO calibration will get me there.

Do you know if the VCO parameters collected at room temp for full assist will hold up over temperature?

Thanks,
John

Hi Dean,

I believe I have full assist mode working correctly. I did an initial calibration to collect all the VCO parameters and I am sending them out with each tune frequency.  I have the associated FORCE bits enabled and I’m not sending out R0.

I’m getting much faster tune times, but I’m seeing a strange result in the transient response. The PLL locks in less than 70 us (< 1 kHz error) but at around 230 us there is a blip that takes the error beyond 1 kHz and doesn’t settle back down again until after 300 us.  When this blip occurs I see the phase (which had been flat) start moving as well.

I tried playing around with some of the different registers variables but nothing helped. In other devices I’ve seen the lock detect timer value cause a similar effect, but adjusting the LD_DLY value had no impact.

My criteria for being locked is less than 1 kHz error so this little blip would prevent me from meeting my 100 us requirement.

For this test, I was hopping between 14 and 8 GHz. The anomaly was more pronounced going to 8 GHz.

I would send some plots, but I didn’t have any luck pasting a picture into this forum last time.

Any idea what I could try to alleviate this glitch?

Thanks,
John

Dean,
Not sending VCO_DACISET helped with the glitch. Reducing the capacitance at pin 3 from 10 to 1 uF almost completely eliminated it. I did still find a glitch with 1 uF on pin 3 (last test case).

I completely removed all the capacitance from pin 3 which got rid of the glitch, but did impact phase noise. I started adding 0.1 uF capacitors to pin 3 and found that 3 in parallel was the most I could tolerate without producing a glitch tune time.

With 0.3 uF on pin 3 there was still a phase noise degradation around 10 kHz, so I opened up the loop bandwidth a little to attenuate the VCO phase noise. Opening the loop bw up from 285 kHz, 65 degrees phase margin (as-shipped) to 400 kHz, 60 degrees phase margin pulled down the VCO phase noise an extra 10 dB at 10 kHz. I made the changes on the eval board and the results appear to be optimal for phase noise and meeting a 100 us tune time.

Since I’m not programming VCO_DACISET, I just left it at the default value (128). Is this the optimal setting VCO_DACISET when not enabling the VCO calibration?