Hi everyone, I am using CDCE6002 chip, but VCO is not locked,also, the profiles of my design are as follows:
1. The input is LVDS and the frequency is 125 MHZ.
2. The output is also LVDS , moreover, the frequency is 25 MHZ.
The phenomenas are as belows:
1. Unlocking occurs, besides, the reading and writing of registers can basically be determined to be normal.
2. The DC bias of the output port is always about 0.4V.
The necessary support as below:
1. Will there be an output clock signal when the chip is not locked? Even if it's wrong.
2. The output is set to LVDS,however, is it normal or not that DC bias is about 0.4V only?
