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Original question:

LMK04828: Dynamic Digital Delay steps

LMK04828: Issue with SYNC_1SHOT_EN

Stephen Miller89
Prodigy 30 points
Part Number: LMK04828

Hi,

I don't think that the SYNC_1SHOT_EN function is working, I was hoping for some feedback. I have a 1 pulse per second signal coming into the SYNC pin that I want to edge align the clocks with. Currently, my programming runs:

Reg 139 -> 0x00, (SYSREF_MUX to normal)

Reg 143 -> 0x51, (SYNC_1SHOT_EN to edge sensitive, SYNC_EN, SYNC_MODE to SYNC pin)

Reg 140 -> 0x00, (enable all blocks)

Reg 144 -> 0x00, (All SYNCs are enabled)

Wait for one second to pass, therefore 1 1PPS signal has time to arrive,

Reg 144 -> 0xff, (Disable SYNCING off clocks,

Reg 139 -> 0x03 (SYSREF_MUX to "continuous".

I have one of the dividers set to 250 MHz, used along with the 1PPS into the LMK to generate my own 1PPS signal, and compare the timing. Between startups, I'm getting a 4 ns variation in timing between the 1PPS in and 1PPS out. Am I missing something?

  • 0
    TI__Mastermind 31120 points

    Hi Stephen,

    Are you controlling the SYNC signal timing in any way? Normal SYNC is re-clocked to the distribution path frequency, so the SYNC signal may be asserted on different distribution clock cycles depending on the timing of the 1PPS edge.

    I notice that SYSREF_CLR is not being asserted. Are you using global or local SYSREF digital delay? SYSREF_CLR must be asserted for at least 15 VCO cycles to clear the digital delay counters, see the datasheet 9.3.2.1.2 and the example just before it.

    Regards,