LMK00334-Q1: LMK00334RTVRQ1 PCIe 2.0 Jitter

A similar question was just asked by another user: https://e2e.ti.com/support/clock-and-timing/f/48/t/843772

After further investigation, there is no max jitter specification for 2.0, only the typical data.

Kind regards,
Lane

Is there a way to conservatively bound the max over temp?  I need to identify a maximum for overall budgeting.   

For PCIE 2.0, the limit is 3.1ps for high frequency jitter and 3.0ps for low frequency jitter. The typical value for high band is 116fsRMS and the typical value for the low band is 27fsRMS. It appears the typical value of 116fsRMS/27fsRMS was the MAX expected jitter. Based on the typical value there is significant margin for PCIE 2.0 link budget. 

Kind regards,
Lane

Great.  What is the input clock slew rate used to obtain those additive jitter numbers?  And how would I extrapolate that jitter number to slower input clock slew rates?

The slew rate was 2.6V/ns . A slower input slew rate would correspond to increased jitter measurement floor, meaning you will see increased jitter due to the influence of the oscilloscope noise and degraded slew rate.

The jitter number reported is post-processed from oscilloscope period data. I'm not certain how one would extrapolate the jitter for different measurement conditions.

Kind regards,
Lane