Other Parts Discussed in Thread: , CDCLVC1112, CDCLVP111
Hello,
we are using the PLL chip LMK04832 for generation of seven clocks (schematic attached). The function in general is ok. All required clocks and timing relationships between them are fine. The only problem we still have and can’t solve by our own at the moment, is a spur in the phase noise of 100MHz clock at 10MHz offset frequency (on PLL CLKout0 and CLKout2). Please see attached measurement diagram.
Some information about the circuit functions:
The PLL generates three 100MHz differential clocks (2x LVPECL and 1x LVDS), one 50MHz LVDS clock and three CMOS 10MHz clocks. In U100 the 50MHz clock is used to generate 10ns pulses with a frequency of 10MHz (LVPECL).
Out problem/tests:
As mentioned above we have to eliminate/reduce the spur at 10MHz offset to at least -140dBc, now it is at about 114dBc. We tried different PLL-settings, but we were not able to eliminate/reduce the spur at 10MHz offset.
What we did:
- We replaced all ferrit beads to Murata BLM18AG601SN1 (about 170 Ohm @10MHz). that improved the phase noise in the range 1kHz-1MHz by about 20dBc, but the spur at 10MHz stayed at 114dBc.
- When we switch of the 10MHz CMOS outputs (PLL out8 out9 and out10), the spur disappears (noise level @10MHz falls to -160dBc).
- When we change the output settings of 10MHz CMOS outputs (PLL out8 out9 and out 10) from “norm/inv” to “norm/norm”, then the spur rises to 104dBc
- When we remove R192 on out8 and switch off out9 and out10 (out8 is ‘free’ running as “norm/inv”), then the spur disappears (-160dBc At 10MHz offset). Whit this configuration, when we attach an oscilloscope probe (10:1, AC, 50ohm termination) to out8_p or out8_n PLL pins, then the spur is again there but with a level of about -142dBc.
- We have also a FPGA in our application. For these test we have deactivated the FPGA and program the PLL via TICS Pro software
Could you please support us with some solution proposals? We could do some additional measurements if needed.
A general question: Is it possible to generate ‘clean’ 100MHz LVPECL and at the same time 10MHz CMOS clocks with the LMK0483? At the moment my assumption is that the 10MHz cause internal or external power bouncing which influences the other outputs or the PLL loops.
Would it help to increase any decoupling caps? We used the capacitor values from LMK04832EVM schematic. Is that enough? Unfortunately we have not found any detailed application notes for the LMK0483. By the way, we see the same behavior as described in #4 also on the LMK04832EVM board.
Thank you in advance.
