LMX2594: Output phase noise vs Reference clock frequency

Sugumar Krishnasamy

Part Number: LMX2594
Other Parts Discussed in Thread: LMX2820

Hi,

We are planning to use your LMX2594 PLL for our wideband freq range of 9000 to 14500MHz.

Our Phase noise requirement at 10KHz offset is -102dBc/Hz. Whereas in you datasheet page No: 14 (Figure 3. Closed-Loop Phase Noise at 15 GHz ) has phase noise -104.8 dBc/Hz at 10KHz offset.

The above phase noise measurement is done Fosc = 100 MHz & Fpd = 200 MHz.

But in our system 10MHz clock will be coming from external for PLL reference. If we use 10MHz clock with phase noise of -175 dBc/Hz at 10KHz offset, The therorical output phase noise at 14.5GHz will be

-175+ 20*log(14500/10) which is around -111 dBc/Hz. But PLL may degrade this level by some amount (Not sure about levels).

1. Is there any huge degradation will be expected if we use 10MHz OCXO O/P to you PLL directly?

2. The Phase noise plots in you datasheets are measured with which 100MHz Reference clock? Can you provide the reference CLK phase noise levels which is used for datasheet measurements?

3. Should we need to use multipliers before PLL ref input to multiply our 10MHz to around 100MHz to meet our requirement of -102dBc/Hz at 10KHz offset?

Our PLL settling time requirement is 100uS (Including PLL write) for your info to consider our loop bandwidth requirements.

Regards,

Sugumar K

over 5 years ago

0 Dean Banerjee over 5 years ago

TI__Mastermind 28021 points

1. There are 3 considerations: a) Noise of our source, b) lower phase detector, c) Slew rate

For the noise of your source, you are -111, so this should be pretty far away. If our 1/f noise is -104.8, so you are a solid 6 dB below this, so this puts you theoretically at -103.9 dBc/Hz.

b) With the lower input reference, you will have a lower phase detector frequency. This raises the PLL flat noise and it could come corrupt your measurement for this lower phase detector frequency. You could use the doubler to double to 20 MHz. This theoretically costs you about 2 dB.

c) The input is sensitive to slew rate. If that's a 10 MHz sine wave, then the phase noise will definitely suffer and degrade. WE don't have the numbers in the LMX2594 datasheet, but there is a nice typical performance graph in the LMX2615 datasheet that shows how the PLL figure of merit and 1/f noise degrade with slew rate and this is what I would expect in the LMX2594 as well.

So to answer your question, I think that you would see on the order of 2-4 dB degradation at 10 kHz offset.

I encourage you to use our PLLatinum Sim tool to get more insight into this.

2. I used a welzel oscillator (501-4623G). At 10 kHz, I measure -160.3 dBc/Hz for a 100 MHz signal

3. Yes, this would be helpful, but ensure they do not add noise. The LMX2594 has an input doubler that is good (OSC_2X). Don't use the programmable multiplier (MULT). It is good for spur avoidance and there is a theoretical benefit, but engaging this input douber adds about 8 dB noise that outweights the theoretical benefit. In summary, use OSC_2X doubler, but if you do, ensure 50% duty cycle.

Regards,

Dean

0 Sugumar Krishnasamy over 5 years ago in reply to Dean Banerjee

Intellectual 420 points

Hi,

We are planning to use pure sine wave reference (50 Ohms load) alone from OCXO. May be we will multiply OCXO output to 100MHz and give it to your PLL reference but still in sine wave.

You have said used wenzel oscillator (501-4623G). At 10 kHz, I measure -160.3 dBc/Hz for a 100 MHz signal. If we calculate theoretical phase noise at 15GHz will be -160.3+20*log(15000/100) which is -116.7dBc/Hz whereas in your datasheet PN curve it is -104.8 dBc/Hz.

1. So around 12dB degradation in PLL? May I know the reason for this? If we need to achieve -102dBc/Hz at 14.5GHz then our reference CLK also should have some excess cushion (10dB)?

2. I am unable to find above Wenzel datasheet in website, Can you share the link?

3. What you are suggesting to achieve -102 dBc/Hz at 14.5GHz using our 10MHz reference OCXO (PN -175dBc/Hz at 10KHz) sine wave output? Should we need to convert our OCXO 10MHz output to 100MHz using frequency multipliers (X2 and X5) and then fed to your PLL?

4. What is the Loop bandwidth used in your eval-board to measure the above datasheet performance?

5. Is there any other PLL to meet our phase noise requirements from 9000 to 14500MHz?

We will try your PLLatinum Sim tool in mean-time to some idea.

Regards,

Sugumar K

0 Dean Banerjee over 5 years ago in reply to Sugumar Krishnasamy

TI__Mastermind 28021 points

Sugmar,

1. PLL has it's own inherent noise. So even with a perfect reference (which the Wenzel is close enough), you will never do better than the -104.8 number (or maybe 0.1 db better or so). This is the 1/f noise of the PLL. So it's not a matter of adding a certain amount the input, but rather a matter of our PLL dominating the noise at thes offset frequencies.

2. I think it has probably been obsoleted and I can't find a link either. But we still have it in the lab. What I do know is that the noise of this reference is lower than our PLL by quit aa bit.

3. If you multiply up the input reference for faster slew rate, this will help our PLL. But be careful that you do not add too much noise in the process of multiplying it up. Theoretocially, you should add 20 dB for an ideal multiplier, so you can add a few dB more than this, but not too much more.

4. For the closed loop plots, about 300 kHz or so. For the numbers for PLL noise, we use a 2 MHz loop bandwidth to measure only the PLL.

5. The LMX2594 is an excellent performance PLL. We will be releasing a new device in the next week or two that has better PLL 1/f noise as well as better VCO noise. The part number is LMX2820, but give it a week or so to show up on the web.

Regards,
Dean

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LMX2594: Output phase noise vs Reference clock frequency