• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 21 subscribers
  • Views 531 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

LMK04828: Making Dynamic Digital Delay work reliably

LMK04828: Dynamic Digital Delay: shift advance to other clocks

Jonas Purtschert
Prodigy 65 points
Part Number: LMK04828
Other Parts Discussed in Thread: , LMK04808

I use the Dynamic Digital Delay to shift the DCLKs.

I followed the example in datasheet SNA605AS p. 44 and programmed the DCLKoutX_DDLY_CNTH/_CNTL (0x101)  according to table 3 and it works to delay the clock.

My Clock Divider is 4, so the CNTH/CNTL is 2/3.

My questions:

1. The datasheet of LMK04828-EP (SNAS703) requires also to program DCLKoutX_DDLYd_CNTH/_CNTL(0x102). Is this also necessary for the LMK04828 (without EP) ?

2. The Table 3 in SNAS605AS  describes CNTH/CNTL register settings only for DELAYING the clock. But what are the values when I want to shift the clock in advance?
In section 9.3.3.2 its just written: "by programming a small alternate divider value ..... "  But A CNTH/CNTL of 1/2 is not allowed.

Thanks for your support,
Jonas

  • 0
    TI__Mastermind 33510 points

    Hi Jonas,

    1. Programming DCLKoutX_DDLYd_CNTH/_CNTL is also necessary for regular LMK04828. It seems this made it into the LMK04828-EP datasheet, but not into the recent LMK04828 update - I'll mark it for the next revision pass. For your reference, the dynamic digital delay may still succeed if the DDLY/DDLYd values are different; the conditions under which differences in these registers cause an unexpected shift are relatively rare, but the unexpected behavior can always be eliminated by making the DDLY/DDLYd registers equal.
    2. For advancing the clock, flip the CNTH/CNTL values of Table 3 and subtract one. Example, for advancing divide of 8: _CNTH=4, _CNTL=3. Because digital delay CNTH/CNTL minimum value is 2, clocks with divide values less than 5 cannot be advanced. Instead, you could delay all other clocks by an equivalent amount.

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 65 points

    Hi Derek,

    Thank you for your clarifying answers!

    I have a follow up question to point 2:

    With our clock divider of 4, we tried out the settings for CNTH/L as if we had a divider of 8:

    Shifting the clock forward and backward was repeatable at first tests.
    Do you know what the drawbacks/problems might be in this case?

    Getting back to the same phase when we shift forward and backward is important for us.

    Regards,
    Jonas

  • 0 in reply to Jonas Purtschert
    TI__Mastermind 33510 points

    Hi Jonas,

    Since dynamic digital delay substitutes the clock with alternate divide values for one cycle by manually choosing when the high/low portions of the output are generated, setting a divide by 4 as though it is a divide by 8 will result in a single clock cycle on the selected output that is double the period of the desired output, ±1 VCO cycle for delay (+) or advance (-). If your application can tolerate this, doubling the effective divide and subtracting one VCO cycle will have the desired effect of advancing the phase by one VCO cycle.

    The LMK04828-EP datasheet cautions against changing the values of CNTH/CNTL registers after programming, but I am not aware of the specific cases where ignoring this restriction results in unexpected behavior. I will investigate the origins of this requirement tomorrow and report my findings. Regardless, it seems that delaying the other clocks is the recommended solution (assuming there is no restriction preventing you from delaying the other clocks).

    I also recommend you take a look at the LMK04808 or equivalent devices in the same family. The dynamic digital delay feature is well-documented on this product, and there is a mechanism for arbitrary advance or delay of the phase of one clock with respect to another. If the LMK04828 dynamic digital delay restrictions and your application needs prevent the kind of reliable phase advance/delay you describe, the LMK0480x family could be the better option.

    Regards,

  • 0 in reply to Derek Payne
    TI__Mastermind 33510 points

    Hi Jonas,

    I found out why static/dynamic CNTH/CNTL values cannot be changed after programming:

    During the dynamic digital delay, the values for d_CNTH/d_CNTL are substituted in place of the divider behavior, but the static digital delay counters are still running again in the background (because dynamic digital delay is effectively a SYNC event). So it's possible when the static/dynamic delay values are different that the clock could switch into a divider that is still awaiting delay completion.

    At any rate, as I see it you have two options to dynamically delay or advance the phase if using the LMK04828:

    1. Delay the target clock to delay the target clock phase, and delay all but the target clock to advance the target clock phase. This is what I suggested in the post above. For this to work, the other clocks must tolerate being delayed as well.
    2. Delay the target clock by 1 cycle to delay the target clock phase, and delay the target clock by 3 cycles to advance the target clock phase (you can execute the dynamic delay three times, or set DDLYd_STEP_CNT=3). A consequence of this approach is that the absolute number of clock cycles experienced by the delayed target will be less than the non-target clocks. If your application cares about the total cycle count on the output clocks in addition to the phase between the output clocks, the cycle count mismatch will present an obstacle. 

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 65 points

    Hi Derek,

    Thank you for the detailed information about the digital delay! This helps a lot for better understanding.

    I will go with your proposed option 2.

    We are using the LMK04828 for JESD204b and need 3 ADCs to be in sync. The ADCs are sampling short pulses which are repetitive. So this should work!

    Regards,

    Jonas