LMX2595: LMX2595

Hello Narendra,

It sounds like the amplifier is adding noise to the reference input and therefor that is increasing the noise, I would assume at frequency offsets 10k Hz on the output.

Is this what you are seeing?

Thanks,

Vibhu

Hi Vibhu,

I am generating 13GHz from PLL using the 70MHz Ref.

As you said there is a degradation of about 8dB at the final Output (13GHz) upto about 10KHz.

This corresponds to about 20 dB degradation in  phase noise in reference.

Do amplifiers in saturation in reference path cause so much noise addition. Due to my instrument phase noise measurement constraint.

I am unable to measure this degradation at 70MHz. Is there any other way to measure this saturation effect on phase noise.

Please clarify.

Hello Narendra,

It is possible that the amplifier is adding the noise. Do you have a way to bypass the amplifier or test the LMX device using an alternate source. At lower offset frequencies the PN is dominated by the input source so if you see the degradation under 10 kHz as I mentioned earlier it is because of the input.

Thanks,

Vibhu

Hello Vibhu,

With an alternate source without saturation phase noise is fine.

My doubt was by pushing reference amplifiers into saturation (say 10dB) do their phase noise degrade so as to corrupt the pll phase noise

Hi Narendra,

I am afraid we are not the right person to comment the effect of saturation to an amplifier, if you are using amplifier from TI, suggest you make a post in the Amplifier forum, we have experts there to give you a more concrete answer. 

As Vibhu pointed out, at 10kHz offset, the reference clock will contribute noise to the overall PLL loop, unless the loop bandwidth is much smaller than 10kHz. 

What is the amplifier output level in the linear region? LMX2595 requires only 0.2V input signal, maybe you can consider bypass the amplifier?

Hello Noel,

Thanks will surely check it out in the Amplifier Forum.

One more related Query.

I want to reduce the bandwidth of the PLL to 3KHz or lower.

But it is not possible with the PLLatinum software with realizable R & C Values. Even at 40KHz BW there is a hump which seems to not come down with any R & C values.

I have attached the simulation files please have a look and suggest values to reduce band with and a steep fall in slope from 6 KHz onwards.

Thank you

Hello Noel,

But if we reduce the loop current and phase det frequency. The phase noise degrades.

How do we balance this.

I have attached a sample simulation.

Please have a look and reply

Hi Noel,

With a reference frequency of 70MHz and using the doubler, PFD=140 MHz.

What is the minimum loop bandwidth that can be set to get best phase noise and sharp roll off at lower offset.

It would be great if u can share a sample simulation.

Hi Narendra,

What is your phase noise requirement?

Hello Noel,

For one of our projects we are experimenting with the LMX2595 chip.

The reference OCXO is same. We have evaluated one more chip from a different company(discrete PLO and VCO) the phase noise plot is as attached. how do i get a similar low bandwidth of loop filter and similar phase noise specs.

Regards

Narendra

Thank you so much for the input Noel