Compiler/LMK04828BEVM: LMK04828BEVM

Hi Basavakiran,

Is this thread related to the same question? 

As I mentioned in the other thread, divide by 1 is an odd divide, which requires duty cycle correction to be enabled; make sure DCLKout#_MUX = 0x01 for "Divider+DCC+HS".

I would like to avoid duplicating E2E threads if possible, so I will mark this thread as resolved and continue in the other thread. If the linked thread is a separate issue from your issue, you are welcome to continue troubleshooting in this thread.

Regards,

Hi Derek Payne

when i used divider+DCC+HS then i'm not unable to fix or modifying delay in output. and i'm not gettnig smooth output signals in signal Oscilloscope.

Thanks & Regards

Basavakiran

Hi Basavakiran,

If you switch from divider only to divider+DCC+HS without resetting the dividers (that is, without a SYNC event), the state of the duty cycle correction and half-step circuitry will not be correct, so the output behavior may not be as desired. You must first set the mux to use divider+DCC+HS, then generate a SYNC event to reset the divider circuitry. This should allow the divider output to function correctly.

Regards,