LMK04828: SYSREF / Device clock

Hi Tom,

DCLKout outputs are even-numbered (0, 2, 4, 6, 8, 10, 12) and can only output device clocks. Device clocks are typically higher frequency and have different dividers to form up to seven different output frequencies for each DCLKout output. The device clock paths also include delay controls for each separate device clock frequency.

SDCLKout outputs are odd-numbered (1, 3, 5, 7, 9, 11, 13) and can output either device clocks or the SYSREF divider output, based on the choice made with SDCLKoutY_MUX. If SDCLKoutY selects a device clock as the source, it will select the device clock generated for DCLKoutX, where X = Y-1 (example: SDCLKout1 can output the same device clock as DCLKout0); and the same device clock delays will be applied to both DCLKoutX and SDCLKoutY. If SDCLKoutY selects the SYSREF divider as the source, the output frequency will be the SYSREF divider output frequency. All outputs which select SYSREF as the source will share the SYSREF_DDLY delay, and the local analog and digital SDCLKoutY delays can also be independently controlled for each SYSREF source path.

Functionally, device clocks are always continuous. SYSREF clocks can be continuous or pulsed. The Device Clock/SYSREF relationship is defined for JESD204B as a synchronization standard, more information can be found in SLAP161 JESD204B Overview.

Regards,