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Original question:

ADS52J90EVM: ADS52J90EVM - Different LMK clock outputs

LMK04826: Questions about PLL2

Eric Raguzin
Prodigy 130 points
Part Number: LMK04826
Other Parts Discussed in Thread: LMK04821

Hello, I've been using the LMK04826 for a while and I have a few questions after reading through the datasheet a few times:

  • What is the PLL2 calibration routine? It's referenced in the settings for PLL2_N_CAL and PLL2_FCAL_DIS, but it's never expanded on. Is this the routine run while trying to lock PLL2? Or is it something that runs before, regardless of if PLL2 has a valid input?
  • For PLL2_XTAL_EN, what input is this referring to? Does this mean that if the input to OSCin is a crystal rather than a VCO, this bit needs to be high? Or is it another input that's not OSCin? CLKin0 or something else?
  • The LMK04826 has the "dual" VCO architecture. But in practice you only choose VCO1 or VCO2. I'm confused at how Figure 11 in the data sheet portrays the two VCOs as integrated somehow. When it seems like for the LMK04826, it's more like Figure 10, just without the "VCO1_DIV" block. Is that right?

Thanks.

  • 0
    TI__Mastermind 28550 points

    Hello Eric,

    Eric Raguzin said:
    What is the PLL2 calibration routine? It's referenced in the settings for PLL2_N_CAL and PLL2_FCAL_DIS, but it's never expanded on. Is this the routine run while trying to lock PLL2? Or is it something that runs before, regardless of if PLL2 has a valid input?


    This is the processing of selecting a capacitor to lock the integrated LC VCO with a nominal Vtune voltage.  For example, if you were to re-configure the device to the same frequency with different settings due to changed OSCin.  There would be no reason to re-run the calibration.  PLL2_N_CAL is normally the same as PLL2_N.  However when using 0-delay mode, the VCO calibration still happens in non-zero delay mode.  Then the PLL switches to use the output of the clock selected for zero delay feedback into the N divider.  This means that two N dividers are needed.  One during calibration (PLL2_N_CAL) and one during operation (PLL2_N).

    Eric Raguzin said:
    For PLL2_XTAL_EN, what input is this referring to? Does this mean that if the input to OSCin is a crystal rather than a VCO, this bit needs to be high? Or is it another input that's not OSCin? CLKin0 or something else?


    Correct, if using a crystal this bit should be high.  Datasheet electrical specs give specs for the crystal.

    Eric Raguzin said:
    The LMK04826 has the "dual" VCO architecture. But in practice you only choose VCO1 or VCO2. I'm confused at how Figure 11 in the data sheet portrays the two VCOs as integrated somehow. When it seems like for the LMK04826, it's more like Figure 10, just without the "VCO1_DIV" block. Is that right?

    With the VCO1 of LMK04821, there is an VCO post divider (VCO1_DIV) which reduces the maximum frequency of VCO1 output.  In LMK04826, you will select either VCO1 or VCO2 - there is no reduction in frequency range.  Figure 11 is correct.

    73,
    Timothy