ADS52J90EVM: ADS52J90EVM - Different LMK clock outputs

I'm evaluating the ADS52J90EVM board with the TSW14J56 FPGA board. I'm interested in testing out some alternative clock speeds. It looks like all of the default scripts on the HMC-DAQ GUI software bypass the PLL on the LMK chip. From the register settings, it seems like they take in the 40 MHz oscillator on the EVM board through CLKin1 and pass it through or divide it down to 10 MHz, without ever using the PLL. I'm interested in trying to use the LMK's PLL to output higher clocks, say 80 MHz or 100 MHz. I'm running into 2 issues:

1. I've been able to force holdover mode in the LMK so that the PLL1 output is the DAC of my choice. I can probe and measure that the control voltage to the CVHD-950-100.000 VCO on net "CP1" is changing with my DAC register settings in the LMK chip. However, whether the VCO VCTRL voltage is 1V or 1.6V or 2.4V, it only ever outputs a 100 MHz reference clock. Is this the correct behavior of the VCO?
2. Even with the unchangeable 100 MHz input into OSCin on the LMK, I should be able to use PLL2 inside the LMK to distribute that clock to the Device and SYSREF clock outputs of the chip. However, I can't get PLL2 to lock with that incoming 100 MHz. I've made sure that the settings are correct so that PLL2_N_MUX and VCO_MUX are completing the loop, I made sure that the PLL2 R and N values should have VCO0 or VCO1 in its specified frequency. But the PLL2 just never locks. Are there any example scripts in the HMC-DAQ GUI format that actually use the LMK chip's PLLs that I could use as a reference?

Thanks.