• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 21 subscribers
  • Views 277 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

LMK04821

LMK04828-EP: External oscillator for PLL1

Igor Tsimerman1
Prodigy 30 points
Part Number: LMK04828-EP
Other Parts Discussed in Thread: LMX2582, CDCM6208, LMK04828

Hi,

The Question is regarding the external oscillator frequency recommendation  We have a reference frequency of 148.5Mhz and 148.35Mhz and would like to create output clocks in the range of 74Mhz-1GHzat 1 Mhz steps and another clock at the frequency of reference clock (148.5M/148.35M). What would be the optimal (jitter and resolution wise) choice for external XO frequency for PLL1 feedback. Can all the output frequency range be achieved with a single frequency? 

Thanks,

Igor

  • 0
    TI__Mastermind 28550 points

    Hello Igor,

    Using this device with an integer N-PLL and integer output dividers will be tricky.  For a moment, let's assume you use only PLL2 and single loop operation with the reference into OSCin.

    - You could produce a buffered output clock OSCin --> OSCout meeting your request for an output clock at the reference clock frequency.  There will be no jitter cleaning, it is just a buffered output clock.

    - Now for the other clock from 74 MHz to 1 GHz.  You will miss 326 to 327 MHz, 466 MHz to 487 MHz, 543 MHz to 588 MHz, 652 MHz to 735 MHz, and 861 MHz to 981 MHz.  With the VCO frequency ranges and the integer dividers there is no way around this.  You will also need to program many VCO frequencies for the outputs you can achieve, there is not a single frequency.  Finally, there will be cases of non-ideal phase detector frequencies.

    If the missing frequencies are ok, we could go to the next step of understand the PLL programming.  However to get 74 MHz to 1 GHz I would suggest the LMX2582.  It supports 20 MHz to 5.5 GHz continuous.  It also has a fractional PLL which means the PLL will be able to operate at higher phase detector frequencies for best performance.

    So for next step, can you advise

     - What are your performance expectations for the reference clock?  Is it ok to simply buffer?
     - Were you expecting jitter cleaning behavior?
     - Do you need only the two outputs?

    The CDCM6208 has a fractional divider and can output frequencies up to 800 MHz.  So no holes, but limited to 800 MHz vs. 1000 MHz.  There may be some other options.

  • 0 in reply to Timothy T
    Prodigy 30 points
    Thank you very much for the prompt reply. We need the following frequencies: 74.25, 79.2, 118.8, 148.5, 158.4, 237.6, 297, 316.8, 475.2, 594, 633.6, 950.4
    So basically, there are two frequencies that falling in-between the VCO ranges: 475.2M and 950.4M. It is an issue and we are checking an option to work around it. In overall we need 4 clocks and their SYSREF at the outputs. In addition, reference clock as well. 
    Regarding the reference clock, I think it should be ok in terms of the jitter from OSCout. 
    I do expect jitter cleaning to the output clocks. Ideally, would like to keep the RMS phase noise upto 150fS.
    I have checked the suggested LMX2582 device. It looks good in terms of the frequencies and fractional dividers. Do you have something like this with 10 outputs and capability for dynamic delay program for each output? upto 100pS step would be fine. preferably - Glitchless. I don't mind if it adds a constand delay like an 500pS analog delay in LMK04828.
    Thanks,
    Igor
  • 0 in reply to Igor Tsimerman1
    TI__Mastermind 30710 points

    Hi Igor,

    The fractional frequency synthesizer products like LMX2582 are all low output count. Your best bet is some combination of devices, where a fractional frequency synthesizer that can hit every frequency in your desired plan is paired with a high output count fanout like LMK04828 which can provide the analog delay steps and the SYSREF distribution.

    I recognize an email from you about the same subject, so I'll try to provide more detailed follow-up later today.

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 30 points

    Thank you very much Derek. I will think on what you have suggested.