• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 169 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

ADS1675: data rate

ADS1675: Is ADS1675 compatible with Arm Cortex based CPUs?

Seyed Sajjad Mirbakht
Prodigy 30 points
Part Number: ADS1675

Hi,

I am going to buy ADS1675 for a medical based high-frequency ultrasonic application but I'm struggling to find answers to these two questions:

1) I will use ADS1675 for digitalizing a signal with a 2MHz frequency, based on the Nyquist theorem my sampling rate should be at least twice the maximum frequency ( >=4MHz). Do you think the oversampling feature of Delta-Sigma architecture would recompensate for the low sampling rate (4MSPS)?

2) Is this ADC compatible with ARM-based CPUs like nRF52 regarding the interface?

Thank you,
Sajjad

  • 0
    TI__Mastermind 37570 points

    Hello Sajjad,

    The ADS1675 includes a digital filter that has a -3dB frequency of 1.9MHz.  At 2MHz, it will attenuate the signal by 6dB, or by 50%.  You can use it to sample an input signal at 2MHz as long as you account for this additional attenuation.

    Also, since the Nyquist limit of 2MHz is in the passband of the digital filter, you can still get some aliasing.  For example, an input frequency of 2.04MHz will alias back to 1.96MHz with an attenuation of about 8dB.  Input frequencies of 2.3MHz or greater will be in the stopband of the filter with more than 115dB of attenuation.  If you expect input signal frequencies with large amplitudes in this stopband, you will need to account for these aliased signals.

    Regarding the interface, in order to support the maximum data rate of 4Msps, the device must operate in LVDS mode which uses the internally generated  clock of 96MHz.  Most processors do not support LVDS level's, but you can use an LVDS-CMOS buffer if needed.

    The host processor also must be able to synchronize to the DRDY signal and accept data using the ADS1675 generated SCLK rate of 96MHz.  Most MCU's cannot meet these timing requirements, and to my knowledge, an FPGA is almost always used in this case. You would need to work directly with the MCU support team to figure out if it would be suitable for your specific processor.

    Please refer to Figures 1 and 2 in the datasheet for specific timing details.

    Regards,
    Keith Nicholas
    Precision ADC Applications