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TLC5540: Need the IBIS model to check the Clock signal quality.

RAHUL JHA
Prodigy 210 points
Part Number: TLC5540
Other Parts Discussed in Thread: ADC3543

Hi All,

We are using the above mentioned ADC part in our current project. This ADC is having a clock signal. This clock signal is driven by a inverting buffer and it is going to 4 ADC parts. We want to check the quality of this clock signal for which we need IBIS model for input clock section. Is it possible to have IBIS model for ADC part? If yes please do share. How we can check this clock signal? Please provide your suggestion. If possible can you suggest any alternate parts to check clock signal?

Regards,

Rahul

  • 0
    TI__Intellectual 1950 points

    Hi Rahul,

    what are you using as a clock source?  crystal oscillator? Do you have a scope/spectrum analyzer to look at the signals after the buffer?

    Please have a look at ADC3543 (https://www.ti.com/product/ADC3541?keyMatch=ADC3543) it's a newer part and has better performance. 

  • 0 in reply to Miguel Lomeli
    Prodigy 210 points

    Hi MIguel,

    Thanks for your response. 

    The main source is 32MHz crystal oscillator. Then it is going to PLL (8MHz output), delay lines and finally driven by a single inverting buffer. This inverting buffer (8mA drive strength) is driving the 8MHz clk to 4 ADC. That is our main concern here. We want to see the clk quality at each ADC. The total trace length is around 8 inches. We are still in designing phase so we can do only pre SI simulation.

    Alternate option is to find an similar kind of buffer which matches the logic and load characteristic as same as ADC clock input pin. This may be time taking but not sure. The part number you shared do not have IBIS model. Any other suggestive part which have similar characteristic and do have a IBIS model?

    Regards,

    Rahul

  • +1 in reply to RAHUL JHA
    TI__Intellectual 1950 points

    Hi Rahul,

    unfortunately, we don't have IBIS model for low frequency parts. As long as the buffer meets the VIH/VIL requirement for the Clock, device will work. Another suggestion can be look at the trace loss(insertion loss) from buffer to clock input and verify that the output buffer swing can accommodate for loss.

  • 0 in reply to Miguel Lomeli
    Prodigy 210 points

    Hi Miguel,

    I checked with similar input buffer with same input logic characteristic. The signal looks good but it will get me more confidence if I get the same IBIS model. Parameters like load capacitance and RLC components is hard to match.