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ADS9120: ADS9120 - How to clock only 16 bits (NOT 20)

Part Number: ADS9120

I need to use the standard SPI interface for the ADS9120, reading the converted data in 16 clock cycle. (not 20)

Table 5 lists # of clock cycles as 16, for optimal read frame.

However, figures 57 & 59 show 20 clocks (D0 to D19)

Are here any APP Note (timing diagrams) that show how to read the converted data with 16 clock cycles?

  • Hello Ramin,

    I do not think we have an app note that specifically shows a 16b conversion result read cycle, but it will be the same as Figures 57/59 depending on the SPI mode you are using.  The first 16b's that you clock out of the device on SDO are the 16b conversion result.  After the 16th bit has been clocked out, you can take /CS high.  This will reset the internal logic and the device will be ready for the next data transfer frame.

    Just to be clear, the first bit clocked out is shown as D19, but this bit refers to the MSB of the output data register.  It is also the MSB of the conversion result.  The last 4 bits, D3,D2,D1,D0 are parity bits, and do not need to be clocked out of the device if you do not want 20b transfers.

    This is also called a SHORT COMMAND FRAME when the number of SCLK's are less than 20.  The device will ignore any data clocked in on SDI and treat it as a NOP (no operation) command, but you will still have your 16b conversion result data.

    Regards,
    Keith Nicholas
    Precision ADC Applications