we have done a new design with 8578s IC. we have designed the IC for serial mode of operation my making PAR/SEL=1,DB15=0.we are using CONVSTA and CONVSTAB tied together and from fpga we are making high and low with 10 micro seconds with no oversampling.
SCLK:we are sending it from fpga 20MHz.
CS:we are making low for entire data acquisition time and high after completion of data acquisition.
busy is becoming high only if we tie constaA and convstB..is this correct for serial mode of operation????(if we are not connecting convstA and convstB ,BUSY pin is always low)
also frstdata pin is becoming high for only for one sclk cycle but data sheet mentions that 14 sclk cycles.
please help us how to proceed in this situation for data acquisition.
