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ADS124S08: ADS124S08

Part Number: ADS124S08

DRDY pulse is continuously high, the sclk i am sending is 3 Mhz, start/sync pin i am making it high ...but i could not able to see DRDY low even after 24 tclk cycles.

i am programming the IC from FPGA.Chipsel and reset are hardwired to 0 and 1.

Initially iam programming all the registers through din and i am making start/sync pin high.but i could not able to see drdy low.

Request you to help us

  • Hi Ponraj,

    Do you have a schematic that you can send me showing how you have things connected?  Are you able to read back the registers to verify that the configuration has been written correctly?  Do you have any scope or logic analyzer shots of the communication that you can share?

    If the RESET pin is high, and all power supplies are valid (AVDD, DVDD and IOVDD) you should see DRDY pulsing at the nominal default data rate if the START/SYNC pin is high.  You should try to verify this prior to communication to the ADS124S08 as this will verify that the device is a functional state.

    Best regards,

    Bob B