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ADS124S08: ADS124S08

Mojtaba Aghaalian
Prodigy 10 points
Part Number: ADS124S08

Hi;

I am reading all Zeros when issuing SFOCAL command. Is that normal? I expected to read a number, as small as it could be, but still a number. I am wondering if there is something wrong with my setup or how I read the SFOCAL register. Please advise. 
Mojie 

  • 0
    TI__Guru** 113765 points

    Hi Mojie,

    You will generally see codes relative to the noise of the ADC in the OFCAL registers after issuing the SFOCAL command.  The most common issue when running the SFOCAL is you must be in conversion mode when the command is issued.  If the ADC is in the idle state, the command will have no effect.  

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 10 points

    Hi Bob; Thank you for getting back to me so quickly. Yes, per the state diagram in the datasheet, the state machine is forcing the ADC in conversion mode when calibration commands are executed. Global chop is disabled as well when SFOCAL command is sent out......... Normal ADC conversion also has been verified thru command scheduler and read of conversion registers. However, SFOCAL always reads zeros. Sounds like you do expect to see non-zero. 

  • +1 in reply to Mojtaba Aghaalian
    TI__Guru** 113765 points

    Hi Mojie,

    Just so that I completely understand what you are trying to do, can you send me the configuration register settings you are using?  You may be a little bit confused by the state machine diagram.  The default configuration for the ADC is continuous mode, but when the device powers up it is in the standby mode (not powerdown, but standby).  This means the ADC is not converting at power up.  

    In section 9.4.3 it states, "Calibration commands are not decoded when the device is in standby mode."  Also, in the SFOCAL description it states in section 9.5.3.9 of the datasheet "Calibration commands must be issued in conversion mode".  So how do you get out of standby mode and into conversion mode?  Issue the START command (or set the START/SYNC pin high).

    So yes, it will be in conversion mode if continuous mode is the selected configuration, but you must at least START the conversion either by pin configuration or using the START command.

    Section 9.4.3 discusses the standby mode and when the device enters this mode.  In figure 82, you can see that the device enters standby on power up, but to get to conversion mode, either the START/SYNC pin  (if not using this pin make sure that it is tied to logic low)  must go high or the START command must be issued.

    Using an oscilloscope or logic analyzer and monitoring DRDY will help to determine if the SFOCAL is truly working as DRDY should remain high for the amount of time the calibration takes place.  Also, you will see the most change in the OFC registers where the noise is highest.  This occurs when running with PGA enabled at a gain of 128 and the data rate at 4ksps.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 10 points

    Hi Bob; 

    Your answer was very helpful. Talking to FPGA implementation folks, it appears currently, our state machine does NOT issue the START command during the calibration sequence we have. They are updating it to reflect your comments of sending START to get into conversion mode followed by a Calibration command. Do you have a System-Verilog model of the ads124s08 component that we can drop into our simulation environment?

    Thank you again,  

  • 0 in reply to Mojtaba Aghaalian
    TI__Guru** 113765 points

    Hi Mojie,

    Unfortunately we do not have a Verilog model for this device.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 10 points

    Hi Bob;

    What about a Simulink model? Anything we can use to validate our VHDL code?

    Mojie

  • 0 in reply to Mojtaba Aghaalian
    TI__Guru** 113765 points

    Hi Mojie,

    99.9% of the time this device is used with a micro, and then all we have is example code.  Any verification of code is done the hard way by using a debugger and logic analyzer.  In the past we have discussed creating simulation models to the digital interfaces for our devices, but the amount of effort is not rewarding in the end for us.  There are many things we would like to do to make customers get through their projects faster, but we have very limited resources for the vast number of devices we support and many new ones that added each year.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 10 points

    Hi Bob;

    We are making progress after issuing START command and now we are able to read non-zero SFOCAL and SYOCAL values that change with sample size and sampling frequency. Thank you for your suggestion. It worked. Any recommendations on how to decide how many times this calibration should be done and whether RESET command should be also used when calibration is done?

    Mojie 

  • 0 in reply to Mojtaba Aghaalian
    TI__Guru** 113765 points

    Hi Mojie,

    This is a little difficult to answer as it will be somewhat specific to your system design.  In general you want to issue the offset calibration following power up, and after data rate and PGA settings are configured.  Some customers will issue periodic offset calibrations if the ADC is changing operating temperature to remove the affects of the offset drift. 

    Global chopping can be used which will remove the ADC offset by taking two measurements and reversing the ADC inputs between measurements.  The downside here is it requires two measurements, and when cycling the mux reduces the overall throughput.  The advantage is ADC offset is always canceled for every measurement.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 10 points

    Hello my helping TI friend :-)

    Thank you for all your inputs. Making good progress. SFOCAL is well understood, and operation mostly checked. Small offset values are read, and I assume every follow-on calibration command would be using that value. Running a test to verify. 

    My last question has to do with SYOCAL. I understand the path from external REFP0/REFN0 pins to ADC comparator. The datasheet says preferably set that voltage to 1/2 AVDD. Why 1/2? Because it is in the middle of comparator dynamic range? What if they have it tied to a 5v ref voltage on the board, with AVDD also be at 5.0.  What I don't understand is what reference voltage is it comparing it to? Does it compare against the voltage at AVDD? If it does and let's say we have tied REFP0/REFN0 to a 5.0v ref, and AVDD is at 5.0, how does it know what we have done? To me there should be a way of us telling it we have it tied to 1/2 AVDD so then it figures okay 2.5000V reference is coming in, let's measure AVDD and see it is at 5.000, and if not anything more or less than 5.000 is offset from board perspective, which affect AIN  range, AIN offset,, .. 

    Please explain. 

    SFOCAL and SYOCAL are the only two commands implemented and I need to make sure I understand how to use them in the system.

    Thank you so much 

    Mojie 

    PS(if you are in TX, in Dallas, I have been to the plant in Richardson years ago, supporting the digital team,, good memories from back then)

  • +1 in reply to Mojtaba Aghaalian
    TI__Guru** 113765 points

    Hi Mojie,

    Mojtaba Aghaalian said:
    The datasheet says preferably set that voltage to 1/2 AVDD. Why 1/2? Because it is in the middle of comparator dynamic range?

    Setting at AVDD/2 allows for the proper common-mode for the PGA input over all PGA gain settings.

    The ADS124S08 is a Delta-Sigma ADC which is an oversampling ADC that compares the input voltage to the reference voltage.  The output result ends up as a modulator bit stream which is later digitally filtered by a low-pass filter.  This oversampling process with multi-order modulators will force the quantization noise to higher frequencies which are later removed by the digital filter.  The outcome is lower noise and increased levels of precision (repeatability).

    The ADS124S08 is a highly integrated device that includes a 2.5V reference and a PGA.  The PGA cannot drive all the way to the rails, so it has input limitations which narrow as the gain is increased.  If making single-ended measurements, then the PGA must be disabled and bypassed so that the measurement can go to the supply rails.

    The input voltage is compared to the reference voltage selected.  This could be the internal reference or some other externally connected reference.  The reference input must be no greater than AVDD.

    What may be adding to the confusion is there are also supply and reference comparators that are comparing these voltages for status information.

    Mojtaba Aghaalian said:
    What if they have it tied to a 5v ref voltage on the board, with AVDD also be at 5.0.  What I don't understand is what reference voltage is it comparing it to? Does it compare against the voltage at AVDD? If it does and let's say we have tied REFP0/REFN0 to a 5.0v ref, and AVDD is at 5.0, how does it know what we have done?

    The conversion result will always be with respect to the selected reference.  The best way for me to explain would be to give a sensor example.  Let's say we have a bridge measurement (a load cell for example) that is powered by the same supply as the reference (5V).  The output of the bridge when idle (no strain) will be 1/2 of 5V with respect to ground for each output (+ to ground and - to ground).  With no strain on the bridge the output will be 0 (+ = - for a balanced bridge) in theory.  But in practice the resistances in each leg will differ slightly and there could be an offset.  Using the SYOCAL will take into account this offset as a part of the system calibration.

    In the end, using the system calibration you need to have the system apply what would be considered a '0' input within the input range of the the ADC.  In the end I actually see this command seldom used.  One reason is that it is complicated to setup and the other is that the conversion outcome for a sensor that has offset is easily handled in code.  Using SFOCAL removes the offset of the ADC which is typically far more important due to drift of the ADC.  SFOCAL will automatically short the inputs together at mid-AVDD supply.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 10 points

    Hi Bob;

    Excellent, Thank you. You answered all my questions. 

    Appreciate all your help.

    Mojie