DRDY pulse is continuously high, the sclk i am sending is 3 Mhz, start/sync pin i am making it high ...but i could not able to see DRDY low even after 24 tclk cycles.
i am programming the IC from FPGA.Chipsel and reset are hardwired to 0 and 1.
Initially iam programming all the registers through din and i am making start/sync pin high.but i could not able to see drdy low.
Request you to help us