ADC32RF45: CMOS SYNCB prevents SDOUT from working

John Polak

Part Number: ADC32RF45

I am using ADC32RF45 on a board of my own design. I would like to use the single ended SYNCB signal to pin 63.

When I write Jesd Digital page register 6036h to the value 40h to assert the CMOS SYNCB setting, then I can no longer complete SPI reads from the ADC. I have probed the SDOUT pin and observed no activity. When I set that register back to 0h, SDOUT starts working again.

I do not observe this behaviour when I set that bit high for register 7036h.

What could be causing this problem?

over 2 years ago

0 Rob Reeder over 2 years ago

TI__Mastermind 20180 points

Hi John,

Give me a few days to work on this. I am talking to the design team to see if they have any thoughts.

Can you please share your schematic with us? That may help us debug the issue.

Regards,

Rob

0 John Polak over 2 years ago in reply to Rob Reeder

Prodigy 141 points

Hi Rob,

Here is the schematic page for the ADC32RF45 in my design.

+1 Vijayendra Varma Siddamsetty over 2 years ago in reply to John Polak

TI__Genius 10505 points

Hi John,

The necessary SPI sequence to enable CMOS sync is:

1. Access the page 0x690000

0x4001 0x00

0x4002 0x00

0x4003 0x00

0x4004 0x69

2. Keep CH=1, and set bit <6> of reg 0x36, and bit <0> of reg 0x3C to '1'.

0x7036 0x40 // bit <6>

0x703C 0x01 // bit<0>

)

Device detects SYNC request at pin# 63 with logic threshold of 600mV ( logic 0 upto 600mV, logic 1 for 600mV to 1.8V).

NOTE : You don’t need to write into the 6036 (register address)

Regards,

Vijay

0 John Polak over 2 years ago in reply to Vijayendra Varma Siddamsetty

Prodigy 141 points

Hello Vijay,

This resolves the SDOUT problem, by simply not writing that bit high in register 0x6036.

As I study the datasheet further (version SBAS747C – MAY 2016 – REVISED DECEMBER 2016), I find that it is inconsistent. I had been thinking that the JESD digital page registers with addresses 0x60.. where for channel A (CH bit is low), and registers with addresses 0x70.. were for channel B (CH bit is high) as desribed in Table 27. However in text on pages 62 and 63, and in Figure 123 the opposite states for the CH bit are described.

Should CH bit be high or low for accessing channel A?

+1 Vijayendra Varma Siddamsetty over 2 years ago in reply to John Polak

TI__Genius 10505 points

Hi John,

For JESD digital page channel selection, CH=0 selects channel B and CH=1 selects channel A. What's given in Figure 123 is correct.

But Table 27 is incorrect regarding this. We will update this in the next revision of the datasheet.

Regards,

Vijay

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ADC32RF45: CMOS SYNCB prevents SDOUT from working