Hello,
I have seen in the datasheet some specific information :
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11.1 Power-Up Sequencing
Before device power up, all digital and analog inputs must be low. At the time of power up, keep all of these
signals low until the power supplies have stabilized, as shown in Figure 76.
Allow time for the supply voltages to reach their final value, and then begin supplying the master clock signal to
the CLK pin.
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When I look at the Evaluation Kit schematic, The external oscillator has it's enable pin connected to VDD, so the clock is driven as soon as the power supply is present.
There seems to be some confusion betwwen the datasheet and the evaluation kit schematic. What is the correct information ?
Also, I didn't checked all the analog and digital signal of the evaluation kit one by one, but just with the schematic, I can see some opamp that must drive their output as soon as the power supply is applied.
So is this requirement to keep all the signal low during power stabilization is respected with the evaluation module ?
Thank you
Stephane
