Hello Team,
Our customer is considering using DAC8411 @ VDD = 4V with a 3.3V SPI.
What is the Serial clock frequency in this case, 20MHz or 50MHz?
I think it is 50MHz on the datasheet, is that correct?
Regards,
Masakazu
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Hello Team,
Our customer is considering using DAC8411 @ VDD = 4V with a 3.3V SPI.
What is the Serial clock frequency in this case, 20MHz or 50MHz?
I think it is 50MHz on the datasheet, is that correct?
Regards,
Masakazu
Hello,
The device will support a clock frequency of 50MHz at VDD = 4, but the timing requirements must still be met with respect to VIH and VIL. The timing requirements are timed from a voltage level of (VIL + VIH)/2 where VIH = 0.7VDD and VIL = 0.3VDD.
For example, the SCLK high time is measured when SCLK rises past 2V. So make sure that this is held for 10ns. Make sure SCLK is held below 2V for 10ns to meet the SCLK low time requirement. This might require a slightly slower SCLK or a non 50% duty cycle.
Best,
Katlynne Jones
Hello Katlynne,
Thanks. By the way customer use to 3.3V as a DIN signal when "timed from a voltage level " is 1.65V?
Or should "timed from a voltage level " be based on VDD ((0.7VDD * 0.3VDD)/2)?
Regards,
Masakazu
Hi Masakazu,
It should be timed from a voltage level based on VDD: ((0.7VDD + 0.3VDD)/2). Which is 2V for a VDD of 4V.
Best,
Katlynne