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ADS1262: programming and calibration commands

Ponraj Tamil
Prodigy 170 points
Part Number: ADS1262

Dear sir,

Request you to help me with the following queries:

I am Programming the IC from FPGA.

note:

1.RESET/PWDN pin always high, and using internal reference ,continuous conversion, gain 32, mux reg-- AIN0(POSITIVE ),AIN1(NEGATIVE) and not using commands to read the data

Q1. I am programming the IC from FPGA with following steps:

step 1. start(pin)=0.

step 2:writing to power register

step3: writing to interface register

step4: writing to mode0 register

step5:writing to mode1 register

step6:writing to mode2 register

step7:writing to inputmux  register

step 8:start(pin)=1 and stopping the sclk.

step 9:waiting for drdy to low, if low go to step10 otherwise in step 9

step 10:read the data 32 bit.......starting the sclk and send 32 sclk cycles to read

step 11:going to 8.

If i am following the above sequence i am able to read 7FFFFFFF only data .output is not changing when i am moving the input voltage(source +/- 2.5 V).Request you to help me with this problem by suggesting the proper sequence for data acquisition.

Q2.

As far as my understanding is concerned it takes 32 clock cycles to read 32 bits of data from this adc via spi, but data sheet speaks about only 16 cycles for data retrieval with respect to this ic(page no 68, figure 108 ,    point 3).can you elaborate on this a little how to understand this interms of data acquisition.

  • 0
    TI__Mastermind 35141 points

    Hi Ponraj,

    Have you confirmed that the registers being written have actually been written correctly? It would make sense to read back the entire register map after your initialization routine to be sure.

    Also, what signal are you applying to the ADC, and what are your power supplies (AVDD, AVSS, DVDD)? Did you say +/-2.5V is the input voltage?

    For your second question, this is just saying that the data needs to be completely read out of the ADC at least 16 tCLKs before DRDY drops low again. This is basically a timing restriction. If you are still clocking out data within 16 tCLKs of DRDY dropping low, that data may be invalid. You absolutely do need to issue 32 SCLKs in order to get data from the ADC each time.

    -Bryan