Hi, I originally opened up a TI support case, but they suggested I post this here. (Case #CS0742865)
We have purchased a total of 5 DAC38RF89EVM’s. 2 are labeled “Rev E”, and 3 are labeled “Rev F”. Two of the “Rev F” boards are now failing. They were previously working fine and have not been modified since. We modified all 5 boards for in-system programming by our host KC705 board. We’d like to run our board modifications by you to see if we did something that may have damaged the chip.
Modifications:
- Installed 0 Ohm resistors for R288, R289, R290, R291 and removed the 4 jumpers on J23
- Installed 0 Ohm resistors for R292, R293, R294, R295.
- Installed 0 Ohm resistors for R9 & R10. We configure GPO0 to be the SYNC0 signal.
- We white wire R9 to C27 so that the FPGA can control DAC_RESET. We use an open drain configuration in the FPGA for this signal.
- We ground R177 so that JESD_TRSTB is grounded.
Both of the failing systems were previously working fine, then started showing startup failures later. On one of the failing boards, the DAC becomes extremely hot compared to the working boards. On the other failing board, register 0x7F[14:10] (EFC_ERR) never clears after a DAC reset. Figure 142 in the data sheet tells us to check this register before programming the chip, but I don’t see much documentation on what an “EFC_ERR” indicates. If we just skip this check, the chip holds the SYNC signal low after configuration, but never raises it, even though the FPGA is transmitting the startup sequence.
We have the chip configured for 8-bit mode, sampled at 8GSPS. We’re using an external 250 MHz signal on J4 for our clock reference. The LMK chip is being configured correctly (we have blinking LEDs that show the clock is correct).
Any insight would be helpful.
Thanks,
Jimmy Mumper