AFE5832: Fclk and data have not been aligned

Ao Sun

Intellectual 790 points

Part Number: AFE5832

AFE5832DEBUG2021_1103.docx

I have some problem about serdes AFE5832's lvds data.

1) Help to check the initialize procedure, what the right sequencing?

(1) Set a reset signal (period about 100ns) after power on

(2) wait 100ns, than set register via spi interface,

#1 spi_data <= 24'h00_0000;

Must write 1

#2 spi_data <= 24'h03_0010;

#3 spi_data <= 24'hD1_0007;

#4 spi_data <= 24'hD4_0001;

PLL reset

wait for 100us

#5 spi_data <= 24'h41_8000;

#6 spi_data <= 24'h42_8000;

wait for 10us

#7 spi_data <= 24'h41_0000;

#8 spi_data <= 24'h42_0000;

init reg

#9 spi_data <= 24'h01_0000;

#10 spi_data <= 24'h04_0010;

TR_TRIG for 3 ad clock

#11 spi_data <= 24'h03_0010;

set skew mode

#12 spi_data <= 24'h02_0100;

set sync mode

#13 spi_data <= 24'h02_0080;

#14 spi_data <= 24'h15_0009;

#15 spi_data <= 24'h21_0009;

#16 spi_data <= 24'h2D_0009;

#17 spi_data <= 24'h39_0009;

#18 spi_data <= 24'hC7_0000;

set sync mode

#19 spi_data <= 24'h02_0380;

set normal mode

#20 spi_data <= 24'h02_0000;

(3) if need to change register after init procedure

#1 spi_data <= 24'h00_0000 or 24'h00_0010 ;(ADC or TGC reg)

#2 spi_data <= register addr and value.

2) Attached file to the problem about lvds serdes

Do you have any other advice? I look forward to your reply. Thanks a lot.

over 2 years ago

0 Praveen Aroul over 2 years ago

TI__Mastermind 49666 points

Hello Ao,

We would like to take this conversation offline since the device AFE5832 is covered under selective disclosure.

Can you please reach out to support_us_afe_tx@list.ti.com along with a reference to this e2e post?

0 Huang Lucas over 2 years ago in reply to Praveen Aroul

Prodigy 50 points

Hi Praveen Aroul,

Ao helped me to send this question, I add some more

i give the adc clock 80Mhz. set 12bit, x1 rate.

1) I serdes FCLK by DCLK ，the value 111111111111000000000000 is very stable under sync mode. But not at ramp mode.

at sync mode the fclk stably:

at ramp mode the fclk instably:

2) My power up sequence shows by Ao , Could you help me to check it?

3) i tried two ways to serdes lvds data as below:

(1) i use sync test pattern 111111000000 , then set delay time in and bitslip the data line . after that, it can match the value well , but the data is wrong by change to ramp mode.

(2) i serdes FCLK, bitslip FCLK and DATA to let FCLK match 111111111111000000000000. but the data not the same in the same chip.

4） what the right power sequence?

i look forward to your reply. thanks.

0 Huang Lucas over 2 years ago in reply to Praveen Aroul

Prodigy 50 points

and what the situation to use the tx_trig signal ? I only use it during power sequence.

0 Praveen Aroul over 2 years ago in reply to Huang Lucas

TI__Mastermind 49666 points

Hello Lucas,

Can you send the queries to the mailing list support_us_afe_tx@list.ti.com?

0 Huang Lucas over 2 years ago in reply to Praveen Aroul

Prodigy 50 points

OK ,thanks a lot.

0 Abhishek Vishwa1 over 2 years ago

TI__Expert 6790 points

Hi Ao,

Since we are supporting this request over mail due to NDA restrictions, I am closing this thread and we can continue the discussion over mail.

Thanks & regards,

Abhishek

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AFE5832: Fclk and data have not been aligned