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ADS1274: Should the SCLK frequency always be lower than CLK frequency in SPI mode? Why?

John11513
Expert 5450 points
Part Number: ADS1274
Other Parts Discussed in Thread: ADS1278, ADS131A04, ADS131M04

Hi experts,

Based on "TIMING REQUIREMENTS: SPI FORMAT" table in ADS1278 datasheet, this device requires the SCLK frequency be always lower than CLK frequency. I cannot understand why this device has such limitation. The question is this limitation impose a difficulty for designer: the SPI data rate has to be configured at very low speed if the required sample rate is low. For example, provided device is operated in 10ksps, high resolution, SPI mode, this means CLK=5.12MHz and the highest allowable SPI bit rate is 5.12Mbps. CPU has to pay about 37.5% (24*8/512) of time for data reading during each sampling interval. 

As my understanding, CLK is for ADC core, SCLK is for SPI interface, why the max SCLK frequency is limited by CLK frequency?

Thank you!

John

  • 0
    TI__Mastermind 23050 points

    Hi John,

    I believe part of this is for performance reasons as running SCLK at non-integer multiples of CLK could result in intermodulation tones. I understand why you might want to have a faster SCLK, but I think this is just an architectural limitation as this device was created from a core that was intended for streaming continuous data (notice how the frame-sync format is very similar to the I2S TDM type format for audio devices). 

    If this is an issue, you might instead consider using a device like ADS131A04 or even ADS131M04 if you only need to run at lower sample rates!

    Best,

    Zak