Using the ADS1298ECGFE-PDK without the MMB0

**TI EDIT February 20th 2019; FOR GENERAL ADS129x ASSISTANCE, PLEASE SEE NEW BIOPOTENTIAL FAQ LOCATED HERE**

Hi Bunfi,

Welcome to the e2e forum!  The jumper positions for the ADS1298ECGFE-PDK you describe above sound correct to get it working with an external processor.  In this case, I am going to assume you have removed the board completely from the MMB0.  When wiring your processor to the ADS1298 evm, please remember to include a few ground connections between your target board and the ADS1298 board - you can do this by short jumper wires either on J4 (pin 5 or TP8) or J3 (pins 4, 10 and 18).

To get the SPI interface of the ADS1298 working correctly, it is important that the SPI_CS is active through the entire data transmission cycle.  Could you perhaps post a screen shot of your data transmission cycle?  You can also review the screen shots from this post and try to verify that you are communicating with the ADS1298 properly:

http://e2e.ti.com/support/data_converters/precision_data_converters/f/73/p/101941/357897.aspx#357897

Hi Tom,

Thanks for the response.
I still could not read the register, always return 0x00.
Actually, I tried to follow and mimic the same signal as close as possible  with the SPI transmission from previous post with the following link:

http://e2e.ti.com/support/data_converters/precision_data_converters/f/73/p/87497/314152.aspx#314152

http://e2e.ti.com/cfs-filesystemfile.ashx/__key/CommunityServer-Components-PostAttachments/00-00-31-16-49/DevID.gif

The link that you have provided has different delay from the link above.
There is obvious delay between first opcode, second opcode and REG DATA of figure from link above which I could not
see from your link. Is the delay during RREG between first opcode, second opcode and reg data is important ?
Here I attach my screen shot of the SPI which taken by several figures combined together.
The figure only shows the SCK and CS signal.

Thanks once again. Is there anything we need to concern for the firmware prior reading the RREG ?

Best Regards,

Bunfai

Hi Bunfai,

The only thing missing from your scope shot that I can see is the actual data to the ADS1298.  Can you per chance include that as well to help us determine if the data to clock phase relationship is correct?  The delay parameters between certain opcodes is described in the data sheet - I don't believe that is an issue here though.  As a quick sanity check, just configure the part as you normally would and don't try to read the data, let me know if you see a consistent DRDY pulse.   This will at least tell us that the power and GPIO functions are configured correctly.

Hi Tom,

I just able to get the other signals using 4 channels oscilloscope as follow :

Ch 1(yellow): SCK
Ch 2(blue)  : CS
Ch 3(purple): MOSI
Ch 4(green) : MISO

Probably the issue in my SPI setup, as from the figure shows the data out (MOSI) is strange and different compare to

http://e2e.ti.com/cfs-filesystemfile.ashx/__key/CommunityServer-Components-PostAttachments/00-00-31-16-49/DevID.gif

Thanks a lots for the responses.

Best Regards,

Bunfai

Hi Tom,
My SPI setup as follows:
- clock frequency : 500kHZ
- dataOrder : MSB Bit first, LSB  bit last
- clock polarity: SCK is active high
- Clock phase :Sample on leading edge of SCK, shift on trailing edge

Is this setup is OK to communicate with the board ?

Thanks a lots for the help.

Best Regards,

Bunfai

Hi Tom,
You are correct, I have changed the ClockPhase (sample on trailing edge, shift on leading edge)
with the result I could read the ID =0x92.The following is SPI signals:

after read all the register, ID = 0x92 and Config1 = 0x06.
The rest has value 0x00, is this correct ?

Thanks for your helps

Best Regards,

Bunfai

Hi Tom,
Just want to ask futher question.
For the write register (WREG). What should we really need to configure ?
To minimize the power consumption, can we setup the ADS1298 for 2 channels only ?

Thank you very much for the responses.

Best Regards,
Bunfai

Great!

From reset, the registers should read as follows:

(Register, Address, Value)

Bunfi,

You can configure as much as you need - perhaps the data rate, the config registers - whatever your end system needs to function.  Unused channels can be powered down to reduce current consumption.  In that case, you need to be a little careful about which channels you disable.  The SPI interface will allow you to read data from channels 1 through 8 in sequence.  If you only need two channels, disable channels 3-8 and your SPI interface only needs three 24-bit transactions, one for the status register and two for data.  If you choose to use channels 7 and 8, your SPI interface needs nine transactions - you can't ignore channels 1-6.

Tom,

There is different registers reading compare to yours.
Config3 = 0x40 and GPIO = 0x1F,Both of them I have got value at 0x00.
Do you have any reason for the different ?
Do need to apply delay in between registers reading (ID..WCT2)?

Thank you very much for your help.

Best Regards,

Hi Bunfai,

At the moment, I can't think of any specific reason why you might be getting something different.  You should not need any delay between reading the registers, so that should not be an issue.  Can you capture an SPI sequence showing just RREG, reading 1 register starting at address 14?

Hi Tom,

I found the issue as you just point out starting address.
For the RREG, the opcode that I use so far start from the first opcode (DIN)
0x20, 0x00, 0xAA, 0xAA, 0xAA..
Note the second opcode should be the number registers to read -1.
I should change the second opcode=0x00 to total registers 26-1=25 (0x19)

After change the second opcode value to 0x19, the result of registers reading as follows:
ID     = 0x92
CONFIG3 = 0X40
GPIO     = 0x0F ( your reading 0x1F) ??
the other registers return value at 0x00.

Just to confirm, reading GPIO bit 4 refer to state of GPIO external pin and
As I disconnect to the MMB0 board, the GPIO1 is not connect to anything.

Many thanks for the help.


Best Regards,
Bunfai

Yes - my GPIO0 is wired to a pull up on the MMB0, which is why I saw 0x1F - with the pin 'open' as in your case, getting 0x0F would be considered normal.  Glad to hear you are up and running!  Have a nice weekend.

Hi Tom,

Thanks clarification and help. I am continuing the write register section.

Have a good weekend.

Best Regards,

Bunfai

Hi Tom

I am also having a problem on reading the ID from ADS1298, but what I diagnosed  seems to be my read time synchronization, as I get different value if I change the order of sequence of my functions.

If it is not too much trouble, can you please have a look of my problem?

http://e2e.ti.com/support/data_converters/precision_data_converters/f/73/p/105592/372311.aspx#372311

Many thanks

Hi Sravan,

Please refer to your original thread:

http://e2e.ti.com/support/data_converters/precision_data_converters/f/73/t/106869.aspx

Hi Rifai Chai 

I am having problem reading the version ID as well, would you mind to share me your hardware set up please?

Weng,

Please continue with the hardware changes we have discussed in email. Many of Rifai Chai's settings are similar to what we have you on track to implement now.

Hi Weng Kou Chan,

You might need to read some previous info on forum regards of ADS1298. 

The following is little bit info what I have done in term of the reading the register ID:

1.   Using the ADS1298ECGFE-PDK (demo kit) to connect to the external  microcontroller 

• Only use the ADS1X98, remove the MMB0 board.
• Use single supply 3.3V apply both AVDD and DVDD
• J4.5 connects to GND (AVDD)
• J4.9 connects to 3.3V (AVSS)
• Jumper JP2 and JP24 open
• Middle pin JP2 connects to 3.3V (DVDD)
• Middle pin J24 GND (DGND)
• JP22 and JP27 open (internal oscillator)
• CS (J3.1) for SPI chip select, JP25 set  to make sure J3.1 connect to SPI_CS
• START( J3.14) connect to output port microcontroller set to high; J26 set make sure J3.14 connect to SPI_START
• DRDY (J3.15) connect to input microcontroller
• DIN (J3.11) connect to microcontroller SPI_DOUT
• DIOUT (J3.13) connect to microcontroller SPI_IN
• JP5 (PWDN) is open

2.   Firmware 

initialization PIO 

P02(Pwrdwn/output)
P06(START/output)
P13(CS/ouput)
P14(sclk/output)
P15(Din/output)
P16(Dout/input)
P12 (DRDY/input)

P02 = 1; //PWRDWM active low, so need high to keep active)
P06 = 1; //START high to begin the conversion
P15 = 1; // din dont care
P14 = 0; // sclk default at low
P13 = 0; // CS default at high

SPI setting

SPI master
Clock Frequency at 500 kHz, tested with 4MhZ still working fine
data Order = MSB bit first, LBB bit last
clock polarity = sclk is active high
Clock Phase : sample on trailing edge of sclk, shift on leading edge

Other info in this forum you may find from Tom posting at

http://e2e.ti.com/support/data_converters/precision_data_converters/w/design_notes/1137.aspx

3.  Firmware for reading register:  To make sure it returns at the same value , use interrupt timer to read the ID or other registers of ADS1298 every seconds

void timer_irq(void) interrupt INTERRUPT_T0 // interrupt 10 ms

{             
      cnt++;
      if (cnt == 100){  // 1 second elapsed                                        
         P13 = 0; // CS low
         delay_us(4);
// RESET Command
         spi_master_read_write(0x06);  
         delay_us(9);
         P13 = 1; //CS high
         delay_us(9);
         P13 = 0; //CS low
         delay_us(4);
//Stop read data continuously mode
         spi_master_read_write(0x11); 
         delay_us(9);
         P13 = 1; //CS high
         delay_us(12);
         P13 = 0; //CS low
         delay_us(4);
                                                   
//RREG command
         spi_master_read_write(0x20); // opcode 1
         delay_us(13);
         spi_master_read_write(0x19); // opcode2
         delay_us(13);

         datain[0] =spi_master_read_write(0xAA);   //return id; AA=dummy byte   
         datain[1] =spi_master_read_write(0xAA); //Config1
         datain[2] =spi_master_read_write(0xAA); //Config2
         datain[3] =spi_master_read_write(0xAA); //Config3
         datain[4] =spi_master_read_write(0xAA); //Lof
         datain[5] =spi_master_read_write(0xAA); //ch1set
         datain[6] =spi_master_read_write(0xAA); //ch2set
         datain[7] =spi_master_read_write(0xAA); //ch3set
         datain[8] =spi_master_read_write(0xAA); //ch4set
         datain[9] =spi_master_read_write(0xAA); //ch5set
         datain[10] spi_master_read_write(0xAA); //ch6set
         datain[11] =spi_master_read_write(0xAA); //ch7set
         datain[12] =spi_master_read_write(0xAA); //ch8set
         datain[13] =spi_master_read_write(0xAA); //rld_sensp
         datain[14] =spi_master_read_write(0xAA); //rld_sensn 
         datain[15] =spi_master_read_write(0xAA); //lof_sentp
         datain[16] =spi_master_read_write(0xAA); //lof_sensn
         datain[17] =spi_master_read_write(0xAA); //lof_flip
         datain[18] =spi_master_read_write(0xAA); //lof_statp
         datain[19] =spi_master_read_write(0xAA); //lof_statn
         datain[20] =spi_master_read_write(0xAA); //gpio
         datain[21] =spi_master_read_write(0xAA); //pace
         datain[22] =spi_master_read_write(0xAA); //resp
         datain[23] =spi_master_read_write(0xAA); //config4
         datain[24] =spi_master_read_write(0xAA); //wct1
         datain[25] =spi_master_read_write(0xAA); //wct2
                    

                     delay_us(9);
                     P13 = 1 ; // CS high
                  

                    uart_puts("\r\n Id = "); uart_puth(datain[0]);         
                    cnt=0;
       }
}

delay above is added because want to mimic the same delay as from previous post:

http://e2e.ti.com/support/data_converters/precision_data_converters/f/73/p/87497/314152.aspx#314152

http://e2e.ti.com/cfs-filesystemfile.ashx/__key/CommunityServer-Components-PostAttachments/00-00-31-16-49/DevID.gif

You can follow as well from the previous post with the different delay setting

http://e2e.ti.com/support/data_converters/precision_data_converters/f/73/p/101941/357897.aspx#357897

It  seems when the delay is removed,  the system still return correct registers reading value as well.Need to double check from the datasheet

which of the correct delays value.

4.  The result of the register reading should return as follows:

5.  The following pictures is the board connection and  SPI data transmission cycle mesure by oscilloscope

5. Testing with TQFP ADS1298 (hand made PCB)

I actually have made ADS1298 testing board with the TQFP version. The schematic you may find in previous post of Josh Wojnas 

http://e2e.ti.com/support/data_converters/precision_data_converters/f/73/p/55907/198417.aspx#198417

The following is my test board connection to the microcontroller port:

And the result is that the testing board return the correct value of registers reading above:

Hopefully this could help.

Best Regards,

Bunfai

Hi Rifai Chai ,

i am having the doubt that are u using the SPI module present in the controller or u are creating the virtual SPI on ur controller.

if u are using the SPI module on the controller then the CS is automatically controlled or u are controlling CS using the GPIO.

regards,

shreedhara