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Original question:

ADS131A04: Driving ADC using external clock input of 25MHz

ADS131A04: 8.192MHz external clock with 3.3V IOVDD

Kazuto Tatsumi
Intellectual 2820 points
Part Number: ADS131A04

Hi team,

My customer is considering the case using 8.192MHz external clock with 3.3V IOVDD even though the recommended value IOVDD >2.7V is 16.384MHz. Could you help me to answer the question below?

  • Q1. Why does the recommended clock become doubled when IOVDD above 2.7V?
  • Q2. What is concern when the external clock is 8.192Mhz with 3.3V IOVDD?

Regards,
Kazuto

  • 0
    TI__Mastermind 18900 points

    Hello Tatsumi-san,

    Let me discuss with the team and get back to you in a day or two.

    Thanks,

    -Cole

  • +1
    TI__Mastermind 18900 points

    Hello Tatsumi-san,

    Q1:

    Talking with the team, its clear that the digital logic within the device can run with a faster clock when the IOVDD is higher. This is why we have split the range to above and below 2.7V.

    That being said, the nominal specification in the recommended operating conditions should be interpreted as "what we usually see in the field". In other words, if the user has IOVDD > 2.7V (or 3.3V), we tend to see them use ~16MHz for their CLKIN signal. Its supposed to give intuition to a user who has never used the devices before.

    Q2:

    With that being said, an experienced customer should just ignore the nominal recommended operating conditions and focus on the minimum and maximum. With this in mind, there is not concern with using 3.3V = IOVDD at 8.192MHz as it falls within the minimum and maximum specifications.

    Best,

    -Cole

  • 0 in reply to Cole Macias
    TI__Intellectual 2820 points

    Hi Cole, thanks for your answer!