I'm using this DAC to bias the front-end channels of a custom ASIC. We've been seeing some issues with oscillations and bandwidth limiting (lower than expected) and through testing we believe that that the DAC's output stage might be involved. The oscillation is likely related to trace lengths and capacitive loading seen at the outputs. The bandwidth effects may simply be the bandwidth limits of the DAC itself.
I'd like to model the whole front-end channel, including the DAC but I can't find a SPICE model for the DAC. If I knew something about the output op-amp stage I could probably just model that rather than the whole DAC but that information is also lacking. Is there any way to get a model for the output op-amp? Or maybe just some specs for the that op-amp stage so I can choose a part with similar characteristics?
