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ADS4229: Receiving data from ADS4229's DDR LVDS mode

Hai Dong6
Prodigy 80 points
Part Number: ADS4229

Hi:

The ADS4229 in LVDS mode sends out data on both clock edge. On the rising edge it send out data from channel 0 and on the falling edge it sends out data from channel 1. 

After I register the data from channel 0 on rising edge and from channel 1 on falling edge, I have to present both data together (to be processed together) . How do I start  receiving data so that data from channel 0 and 1 are lined up (in sync) ? 

For example when in "sync", sample 0 from channel 0 is latched (present together) with channel 1; sample 1 from channel 0 is latched with channel 1; etc. (0,0  ; 1,1; etc.)

When NOT in "sync", sample 0 from channel 0 is latched with sample 1 from channel 1; sample 1 from channel 0 is latched with sample 2 from channel 1; etc.  (0,1 ; 1,2; etc.)

Thanks

Hai

  • 0
    TI__Guru* 91947 points

    Hai,

    Data does not come out Channel 0 first then Channel 1 second like you are describing. The data coming out is even bits followed by odd bits on both channels at the same time. . To get the even bits lined up with the odd bits, you will latch the even bits with two registers and the odd bits one register. The first register used by the even bits will use the rising edge of the CLKOUT and the second register will use the falling edge. The odd bits register will use the falling edge. The second register output of the even bits will now be lined up with the odd bits register.

    Regards,

    Jim