Other Parts Discussed in Thread: TPS22810,
This is a continuation of a previous ticket I submitted (CS0822302). Bob Benjamin has been assisting me. The ADS1220 is powered off, and then power is applied with a Controlled Rise Time Switch (TPS22810). This means the uC is powered during this period. The CS and other SPI (clk, data in, data out) are not initialized until power is applied to the ADS1220. On the CS pin (which is now a GPIO Input), I have enabled the internal pull up on the micro to de-assert the CS with the intent to shield the ADS1220 from inadvertent activity on the SPI (noise, etc). Therefore, while the power is being applied to the ADS1220 (with controlled rise time), the CS voltage follows the ADS1220 power limited by the body diode. There for, the CS voltage is ~0.7 volts higher than the power input and current limited by the internal pullup (47K?). Is this in violation, and will it cause problems?
We then initialize the SPI and send a RESET command to the ADS1220. After 100ms, we check that the DRDY is asserted (Logic Low). On many of our units, this test fails.
Considering all the dynamics here:
- Uc is powered first
- ADS1220 is powered with controlled rise time switch
- SPI is now initialized
- RESET command is sent over SPI to ADS1220
Is there an error in our Power Up sequence?