Other Parts Discussed in Thread: ADS131M06
Hello,
I'm trying to sample data with the ADS131 series chip with a Raspberry Pi. Since the RPi is not a microcontroller and has no real-time capabilities, sampling with good repeatability at high frequencies using an interrupt on the DRDY signal is almost impossible. Therefore, I am using the DMA capabilities of the RPi for sampling without CPU intervention, but it cannot be synchronous with the DRDY signal. I still want to remain in the asynchronous slave mode of the device, since the RPi is not able to output a master clock reliably. Due to some slight clock drift of the RPi (or the ADS), I observe that periodically (depending on the sampling frequency) the SPI transfer occurs when the DRDY signal toggles, raising the F_DRDY bit in the STAT_1 register and not updating new conversion results. This happens until the SPI transfer is again out of the range of the DRDY signal toggling. My guess is that this happens because new conversions cannot be read (by the Pi) and written (by the ADS131) simultaneously in the internal SPI register.
My question is: would this phenomenon also happen on the ADS131M06 chip? From the datasheet it seems that this chip has a small FIFO buffer that would probably allow to read and write new conversion data simultaneously. Is that correct? Also, what happens when this FIFO is full? Are new conversions overwritten or discarded?
Thank you very much in advance.
Best regards,
Nicolas Verbeek