Hi,
We have a custom board with ADC12DJ3200 and Kintex UltraScale FPGA from Xilinx. We are using JMODE 11.
The FPGA code for data capture has been created based on the KCU105 firmware available from TI, the transport layer code and the JESD IP configuration have been modified for JMODE 11.
We tested long transport test pattern and I am expecting the following pattern :
Lane Frame 0 Frame 1 Frame 2 Frame 3
DA0 0003 0002 8000 8000
DA1 0002 0005 8000 8000
DA2 0004 0002 8001 8000
DA3 0004 0004 8000 8001
DB0 0003 0002 8000 8000
DB1 0002 0005 8000 8000
DB2 0004 0002 8001 8000
DB3 0004 0004 8000 8001
According to the Xilinx IP product guide, this is how it should come:
0004000400020004000500020002000300040004000200040005000200020003
8001800080008001800080008000800080018000800080018000800080008000
But when we test, this is how it is coming:
0400040002000400050002000200030004000400020004000500020002000300
0180008000800180008000800080008001800080008001800080008000800080
In the output we're getting, the last 8-bits in the LSB side, seems to be part of DB3 and is expected to come at the MSB side.
When we capture data using this design (instead of pattern test), the spectrum is not proper.
Any help is appreciated.
Thanks!