ADS8900B: Example code for Interfacing with FPGA

Part Number: ADS8900B
Other Parts Discussed in Thread: REF5050, REF5045, OPA376, THS4561, THS4521, THS4505,

Hi.

    I am trying to interface ADS8900 with my FPGA, my plan was to get a EVALUATION BOAD for that ADC and with bit of reverse engineering and probing SPI pins with my logic analyzer, I will be able to get that ADC to talk to my FPGA over SPI comm. 

But due to silicon crysis the delivery date of ordered eval board is keep on postponing in mouser,  So i decided to make my own basic personal basic eval board inspired from schematic provided in the data sheet.  I am attaching my schematic please verify it once and also help me with some VHDL example codes. 
schemetic_eval_01.pdfschemetic_eval_02.pdf

regard

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Pratik  

  • Hello Pratik,

    We do not have FPGA example code for the ADS8900B ADC.  However, you can use a standard SPI-00-S interface to the device for initial development, and then change to quad-SDO if you need to lower the SCLK frequency.  Details are in section 7.5 of the datasheet, and Figures 47 and 48 provide additional detail on the data transfer frame.  If you have problems getting your communications to work, you can post logic/scope waveforms to the forum and we can help debug any timing issues.

    Schematic Review:

    1. The output of the REF5050, U7, needs a minimum of 1uF load capacitance between VOUT (pin 6) and ground for stability.

    2. If using a 5V reference, the minimum RVDD supply voltage for the ADS8900B will be Vref+0.3V, or +5.3V.  Another option is to use the REF5045, 4.5V output, and keep RVDD=5V.  In addition, the REF50xx requires a supply voltage at least 0.2V higher than the output voltage.

    3. The V+ supply (pin 7) of the the OPA376 buffer needs connected to the +5V power bus.

    4. The minimum output capacitance on the REFBUFOUT (pins 5,7) of the ADS8900B is 10uF; increase the 1uF to 10uF capacitor value.

    5. The THS4505 amplifier will not be able to drive the ADC inputs over the full scale input range due to the output voltage limits of the amplifier.  I suggest using the THS4561 or previous generation THS4521, which will be able to support most of the full scale input range of the ADC.  Both of these amplifiers have stock available.

    6. The bypass caps on VS+(pin3) of THS4505 are connected to the ground pin; connect the bypass caps between VS+(pin3) and VS-(pin6).

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • thank you for your answer

    The problem is i already received the REF5050 package and now I don't want to go for another ref IC (4.5v) . can you suggest some alternate 5.3v power supply ICs that are available in stock. 

  • Hello Pratik,

    Any adjustable regulator that has high PSRR (>50dB at 10kHz) will typically work well.  TPS79601 is an older generation device and there is stock on ti.com as of today.

    Regards,
    Keith

  • Hello Keith, 
        some how i am able to get all the relevant ICS ( the REF5050 , TPS 74A700, and ADC) i  thing now i will be able to make my own basic eval board. can you verify my new schematic. i have attached the PDFs of schematics. 

    and not necessarily VHDL if i get a code to interface with ADC in any form (python/C++ for Raspberry pi  beaglebone black) or code for arduino to interface with ADC through SPI please help me with that.


    ref_conn.pdf         adc_and_diffopamp.pdf

    regards

    -------

    Pratik 

  • Hello Pratik,

    1.  Place bypass capacitors C1 and C2 on VS+ pin 10 of IC1.

    2.  Connect /PD pin 3 of IC1 to VS+ pin 10 53_SUP to enable amplifier.

    3. Increase C4 from 1uF to 10uF to meet minimum output capacitance requirement.

    4. Include RC filter between amplifier out pins (pin1 and pin 9) and the ADC inputs (pin10 and pin9).  This is necessary to properly drive the ADC inputs.  Please refer to figure 111 in the ADS8900 datasheet.

    5. Place a minimum 1uF load capacitance on output pin 6 of REF5050.

    6. Include a 0.1uF bypass cap from Pin 7 to ground of OPA376.

    7. Connect Pin 21 (exposed thermal pad) of TPS7A4700 to ground plane.

    8.  In order for the TPS7A4700 to regulate +5.3V on the output, the minimum input voltage needs to be +5.5V (+5 net needs to be set to +5.5V)

    If you have any questions on SPI communications, please post logic/scope waveforms to help with debug.  Also, the ADS8900BEVM-PDK User's Guide provides full schematics for the evaluation board.  You can use these as a guide for your own design.

    ADS8900BEVM-PDK Evaluation Module

    Regards,
    Keith