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ADS42JB49: Single lane data abnormal

Amy Luo
Expert 6895 points
Part Number: ADS42JB49

Hi team,

A query from one of our customers:

When using this ADC chip, the acquisition data is abnormal. Use 204B test mode to send incremental code, burrs on output signal, only single lane present, rest lanes normal.

Best Regards,

Amy Luo

  • 0
    TI__Guru* 91947 points

    Amy,

    Please provide more info. What is the LMFS setting used, what is the sample rate, what value of K is used, SYSREF frequency, what FPGA is used. Customer design, or TI EVM?

    The more you send the more we can help wit this issue.

    Regards,

    Jim